一，HMC7043芯片
MC7043独特的特性是对14个通道分别进行独立灵活的相位管理。所有14个通道均支持频率和相位调整。这些输出还可针对50 Ω或100 Ω内部和外部端接选项进行编程。HMC7043器件具有RF SYNC功能，支持确定性同步多个HMC7043器件，即确保所有时钟输出从同一时钟沿开始。可通过改写嵌套式HMC7043或SYSREF控制单元/分频器，然后重新启动具有新相位的输出分频器来实现。MC7043芯片支持3.2G信号发生。
1，硬件原理图：
（1）HMC7043电路图：
（2）芯片管脚图：
2，芯片读写操作：
（1），读
（2），写
（3），读写时序
（4），寄存器地址参数控制配置
3，控制寄存器映射位描述
4，HMC7043 verilog控制代码
`timescale 1ns / 1ps
// Company:SUBOMB
module HMC7043_CFG #( parameter [11:0] CLKOUT0_DIV = 12'd5 ,
CLKOUT1_DIV = 12'd5 ,
CLKOUT2_DIV = 12'd5 ,
CLKOUT3_DIV = 12'd5 ,
CLKOUT4_DIV = 12'd5 ,
CLKOUT5_DIV = 12'd5 ,
CLKOUT6_DIV = 12'd5 ,
CLKOUT7_DIV = 12'd5 ,
CLKOUT8_DIV = 12'd5 ,
CLKOUT9_DIV = 12'd5 ,
CLKOUT10_DIV = 12'd5 ,
CLKOUT11_DIV = 12'd5 ,
CLKOUT12_DIV = 12'd5 ,
CLKOUT13_DIV = 12'd5
)(
input clk_30M ,
input rst ,
output HMC7043_SEN ,
output HMC7043_SCLK ,
output HMC7043_SDATA ,
output reg HMC7043_RESET = 1'b1 ,
input HMC7043_GPIO //default ,resever
);
// config ad9680 from spi interface//
wire spi_busy ;
reg [7:0] cfg_cnt = 8'd0 ;
reg send_spi_vld = 1'b0 ;
reg [23:0] mem_reg1[22:0] ;
reg [31:0] cfg_delay = 32'd0 ;
//--------------------------------------------------------
initial
begin
// mem_reg1[0] = 24'h001500 ; //anolog input
// mem_reg1[1] = 24'h00160e ; //400 ou
//default
mem_reg1[0] = 24'h009600 ;
mem_reg1[1] = 24'h009700 ;
mem_reg1[2] = 24'h009800 ;
mem_reg1[3] = 24'h009900 ;
mem_reg1[4] = 24'h009a00 ;
mem_reg1[5] = 24'h009baa ;
mem_reg1[6] = 24'h009caa ;
mem_reg1[7] = 24'h009daa ;
mem_reg1[8] = 24'h009eaa ;
mem_reg1[9] = 24'h009f4d ;
mem_reg1[10] = 24'h00a0df ;
mem_reg1[11] = 24'h00a197 ;
mem_reg1[12] = 24'h00a203 ;
mem_reg1[13] = 24'h00a300 ;
mem_reg1[14] = 24'h00a400 ;
mem_reg1[15] = 24'h00a506 ;
mem_reg1[16] = 24'h00a61c ;
mem_reg1[17] = 24'h00a700 ;
mem_reg1[18] = 24'h00a806 ;
mem_reg1[19] = 24'h00a900 ;
mem_reg1[20] = 24'h00ab00 ;
mem_reg1[21] = 24'h00ac20 ;
mem_reg1[22] = 24'h00ad00 ;
mem_reg1[23] = 24'h00ae08 ;
mem_reg1[24] = 24'h00af50 ;
mem_reg1[25] = 24'h00b004 ;
mem_reg1[26] = 24'h00b10d ;
mem_reg1[27] = 24'h00b200 ;
mem_reg1[28] = 24'h00b300 ;
mem_reg1[29] = 24'h00b400 ;
mem_reg1[30] = 24'h00b500 ;
mem_reg1[31] = 24'h00b600 ;
mem_reg1[32] = 24'h00b700 ;
mem_reg1[33] = 24'h00b800 ;
//global
mem_reg1[34] = 24'h000000;
mem_reg1[35] = 24'h000100;
mem_reg1[36] = 24'h000204;
mem_reg1[37] = 24'h000334;//sysref timer enable
mem_reg1[38] = 24'h00047f;//14 channel output enable
mem_reg1[39] = 24'h00050f;//reserved
mem_reg1[40] = 24'h000600;
mem_reg1[41] = 24'h000700;
mem_reg1[42] = 24'h000900;//reserved
//input buffer
mem_reg1[43] = 24'h000a07;
mem_reg1[44] = 24'h000b07;
//sysref
mem_reg1[45] = 24'h005a00;//level control,pluse generator
mem_reg1[46] = 24'h005b04;//SYNC CONTROL
mem_reg1[47] = 24'h005c00;//sysref timer control LSB <= 4MHz
mem_reg1[48] = 24'h005d08;//sysref timer control MSB
mem_reg1[49] = 24'h004600;//GPI1 setting
mem_reg1[50] = 24'h005037;//GPO1 setting
mem_reg1[51] = 24'h005403;//SDATA control
mem_reg1[52] = 24'h006400;//clk input control
mem_reg1[53] = 24'h006500;//delay low power mode
mem_reg1[54] = 24'h007110;//Alarm Mask Control
//clock distribute
mem_reg1[55] = 24'h00c8f3;//ch0 mode,channel enable
mem_reg1[56] = {16'h00c9,CLKOUT0_DIV[7:0]};//ch0 divider lsb [7:0]
mem_reg1[57] = {16'h00ca,4'h0,CLKOUT0_DIV[11:8]};//ch0 divider Msb [11:8]
mem_reg1[58] = 24'h00cb00;//ch0 fine delay step,step size:25ps
mem_reg1[59] = 24'h00cc00;//ch0 coarse digital delay
mem_reg1[60] = 24'h00cd00;//ch0 multislip digital delay,lsb [7:0]
mem_reg1[61] = 24'h00ce00;//ch0 multislip digital delay Msb [11:8]
mem_reg1[62] = 24'h00cf00;//ch0 divider output
mem_reg1[63] = 24'h00d031;//ch0 force mute,nomal,lvds mode
mem_reg1[64] = 24'h00d2f3;//ch1 mode,channel enable
mem_reg1[65] = {16'h00d3,CLKOUT1_DIV[7:0]};//ch1 divider lsb [7:0]
mem_reg1[66] = {16'h00d4,4'h0,CLKOUT1_DIV[11:8]};//ch1 divider Msb [11:8]
mem_reg1[67] = 24'h00d500;//ch1 fine delay step,step size:25ps
mem_reg1[68] = 24'h00d600;//ch1 coarse digital delay
mem_reg1[69] = 24'h00d700;//ch1 multislip digital delay,lsb [7:0]
mem_reg1[70] = 24'h00d800;//ch1 multislip digital delay Msb [11:8]
mem_reg1[71] = 24'h00d900;//ch1 divider output
mem_reg1[72] = 24'h00da31;//ch1 force mute,nomal,lvds mode
mem_reg1[73] = 24'h00dcf3;//ch2 mode,channel enable
mem_reg1[74] = {16'h00dd,CLKOUT2_DIV[7:0]};//ch2 divider lsb [7:0]
mem_reg1[75] = {16'h00de,4'h0,CLKOUT2_DIV[11:8]};//ch2 divider Msb [11:8]
mem_reg1[76] = 24'h00df00;//ch2 fine delay step,step size:25ps
mem_reg1[77] = 24'h00e000;//ch2 coarse digital delay
mem_reg1[78] = 24'h00e100;//ch2 multislip digital delay,lsb [7:0]
mem_reg1[79] = 24'h00e200;//ch2 multislip digital delay Msb [11:8]
mem_reg1[80] = 24'h00e300;//ch2 divider output
mem_reg1[81] = 24'h00e431;//ch2 force mute,nomal,lvds mode
mem_reg1[82] = 24'h00e6f3;//ch3 mode,channel enable
mem_reg1[83] = {16'h00e7,CLKOUT3_DIV[7:0]};//ch1 divider lsb [7:0]
mem_reg1[84] = {16'h00e8,4'h0,CLKOUT3_DIV[11:8]};//ch1 divider Msb [11:8]
mem_reg1[85] = 24'h00e900;//ch3 fine delay step,step size:25ps
mem_reg1[86] = 24'h00ea00;//ch3 coarse digital delay
mem_reg1[87] = 24'h00eb00;//ch3 multislip digital delay,lsb [7:0]
mem_reg1[88] = 24'h00ec00;//ch3 multislip digital delay Msb [11:8]
mem_reg1[89] = 24'h00ed00;//ch3 divider output
mem_reg1[90] = 24'h00ee31;//ch3 force mute,nomal,lvds mode
mem_reg1[91] = 24'h00f0f3;//ch4 mode,channel enable
mem_reg1[92] = {16'h00f1,CLKOUT4_DIV[7:0]};//ch4 divider lsb [7:0]
mem_reg1[93] = {16'h00f2,4'h0,CLKOUT4_DIV[11:8]};//ch4 divider Msb [11:8]
mem_reg1[94] = 24'h00f300;//ch4 fine delay step,step size:25ps
mem_reg1[95] = 24'h00f400;//ch4 coarse digital delay
mem_reg1[96] = 24'h00f500;//ch4 multislip digital delay,lsb [7:0]
mem_reg1[97] = 24'h00f600;//ch4 multislip digital delay Msb [11:8]
mem_reg1[98] = 24'h00f700;//ch4 divider output
mem_reg1[99] = 24'h00f831;//ch4 force mute,nomal,lvds mode
mem_reg1[100] = 24'h00faf3;//ch5 mode,channel enable
mem_reg1[101] = {16'h00fb,CLKOUT5_DIV[7:0]};//ch5 divider lsb [7:0]
mem_reg1[102] = {16'h00fc,4'h0,CLKOUT5_DIV[11:8]};//ch5 divider Msb [11:8]
mem_reg1[103] = 24'h00fd00;//ch5 fine delay step,step size:25ps
mem_reg1[104] = 24'h00fe00;//ch5 coarse digital delay
mem_reg1[105] = 24'h00ff00;//ch5 multislip digital delay,lsb [7:0]
mem_reg1[106] = 24'h010000;//ch5 multislip digital delay Msb [11:8]
mem_reg1[107] = 24'h010100;//ch5 divider output
mem_reg1[108] = 24'h010231;//ch5 force mute,nomal,lvds mode
mem_reg1[109] = 24'h0104f3;//ch6 mode,channel enable
mem_reg1[110] = {16'h0105,CLKOUT6_DIV[7:0]};//ch6 divider lsb [7:0]
mem_reg1[111] = {16'h0106,4'h0,CLKOUT6_DIV[11:8]};//ch6 divider Msb [11:8]
mem_reg1[112] = 24'h010700;//ch6 fine delay step,step size:25ps
mem_reg1[113] = 24'h010800;//ch6 coarse digital delay
mem_reg1[114] = 24'h010900;//ch6 multislip digital delay,lsb [7:0]
mem_reg1[115] = 24'h010a00;//ch6 multislip digital delay Msb [11:8]
mem_reg1[116] = 24'h010b00;//ch6 divider output
mem_reg1[117] = 24'h010c31;//ch6 force mute,nomal,lvds mode
mem_reg1[118] = 24'h010ef3;//ch7 mode,channel enable
mem_reg1[119] = {16'h010f,CLKOUT7_DIV[7:0]};//ch7 divider lsb [7:0]
mem_reg1[120] = {16'h0110,4'h0,CLKOUT7_DIV[11:8]};//ch7 divider Msb [11:8]
mem_reg1[121] = 24'h011100;//ch7 fine delay step,step size:25ps
mem_reg1[122] = 24'h011200;//ch7 coarse digital delay
mem_reg1[123] = 24'h011300;//ch7 multislip digital delay,lsb [7:0]
mem_reg1[124] = 24'h011400;//ch7 multislip digital delay Msb [11:8]
mem_reg1[125] = 24'h011500;//ch7 divider output
mem_reg1[126] = 24'h011631;//ch7 force mute,nomal,lvds mode
mem_reg1[127] = 24'h0118f3;//ch8 mode,channel enable
mem_reg1[128] = {16'h0119,CLKOUT8_DIV[7:0]};//ch8 divider lsb [7:0]
mem_reg1[129] = {16'h011a,4'h0,CLKOUT8_DIV[11:8]};//ch8 divider Msb [11:8]
mem_reg1[130] = 24'h011b00;//ch8 fine delay step,step size:25ps
mem_reg1[131] = 24'h011c00;//ch8 coarse digital delay
mem_reg1[132] = 24'h011d00;//ch8 multislip digital delay,lsb [7:0]
mem_reg1[133] = 24'h011e00;//ch8 multislip digital delay Msb [11:8]
mem_reg1[134] = 24'h011f00;//ch8 divider output
mem_reg1[135] = 24'h012031;//ch8 force mute,nomal,lvds mode
mem_reg1[136] = 24'h0122f3;//ch9 mode,channel enable
mem_reg1[137] = {16'h0123,CLKOUT9_DIV[7:0]};//ch9 divider lsb [7:0]
mem_reg1[138] = {16'h0124,4'h0,CLKOUT9_DIV[11:8]};//ch9 divider Msb [11:8]
mem_reg1[139] = 24'h012500;//ch9 fine delay step,step size:25ps
mem_reg1[140] = 24'h012600;//ch9 coarse digital delay
mem_reg1[141] = 24'h012700;//ch9 multislip digital delay,lsb [7:0]
mem_reg1[142] = 24'h012800;//ch9 multislip digital delay Msb [11:8]
mem_reg1[143] = 24'h012900;//ch9 divider output
mem_reg1[144] = 24'h012a31;//ch9 force mute,nomal,lvds mode
mem_reg1[145] = 24'h012cf3;//ch10 mode,channel enable
mem_reg1[146] = {16'h012d,CLKOUT10_DIV[7:0]};//ch10 divider lsb [7:0]
mem_reg1[147] = {16'h012e,4'h0,CLKOUT10_DIV[11:8]};//ch10 dividerMsb [11:8]
mem_reg1[148] = 24'h012f00;//ch10 fine delay step,step size:25ps
mem_reg1[149] = 24'h013000;//ch10 coarse digital delay
mem_reg1[150] = 24'h013100;//ch10 multislip digital delay,lsb [7:0]
mem_reg1[151] = 24'h013200;//ch10 multislip digital delay Msb [11:8]
mem_reg1[152] = 24'h013300;//ch10 divider output
mem_reg1[153] = 24'h013431;//ch10 force mute,nomal,lvds mode
mem_reg1[154] = 24'h0136f3;//ch11 mode,channel enable
mem_reg1[155] = {16'h0137,CLKOUT11_DIV[7:0]};//ch11 divider lsb [7:0]
mem_reg1[156] = {16'h0138,4'h0,CLKOUT11_DIV[11:8]};//ch11 divider Msb [11:8]
mem_reg1[157] = 24'h013900;//ch11 fine delay step,step size:25ps
mem_reg1[158] = 24'h013a00;//ch11 coarse digital delay
mem_reg1[159] = 24'h013b00;//ch11 multislip digital delay,lsb [7:0]
mem_reg1[160] = 24'h013c00;//ch11 multislip digital delay Msb [11:8]
mem_reg1[161] = 24'h013d00;//ch11 divider output
mem_reg1[162] = 24'h013e31;//ch11 force mute,nomal,lvds mode
mem_reg1[163] = 24'h0140f3;//ch12 mode,channel enable
mem_reg1[164] = {16'h0141,CLKOUT12_DIV[7:0]};//ch12 divider lsb [7:0]
mem_reg1[165] = {16'h0142,4'h0,CLKOUT12_DIV[11:8]};//ch12 divider Msb [11:8]
mem_reg1[166] = 24'h014300;//ch12 fine delay step,step size:25ps
mem_reg1[167] = 24'h014400;//ch12 coarse digital delay
mem_reg1[168] = 24'h014500;//ch12 multislip digital delay,lsb [7:0]
mem_reg1[169] = 24'h014600;//ch12 multislip digital delay Msb [11:8]
mem_reg1[170] = 24'h014700;//ch12 divider output
mem_reg1[171] = 24'h014831;//ch12 force mute,nomal,lvds mode
mem_reg1[172] = 24'h014af3;//ch13 mode,channel enable
mem_reg1[173] = {16'h014b,CLKOUT13_DIV[7:0]};//ch13 divider lsb [7:0]
mem_reg1[174] = {16'h014c,4'h0,CLKOUT13_DIV[11:8]};//ch13 divider Msb [11:8]
mem_reg1[175] = 24'h014d00;//ch13 fine delay step,step size:25ps
mem_reg1[176] = 24'h014e00;//ch13 coarse digital delay
mem_reg1[177] = 24'h014f00;//ch13 multislip digital delay,lsb [7:0]
mem_reg1[178] = 24'h015000;//ch13 multislip digital delay Msb [11:8]
mem_reg1[179] = 24'h015100;//ch13 divider output
mem_reg1[180] = 24'h015231;//ch13 force mute,nomal,lvds mode
mem_reg1[181] = 24'h000102;
mem_reg1[182] = 24'h000000;
mem_reg1[183] = 24'h000100;
end
//----------------------------------------------
always@(posedge clk_30M or posedge rst)
begin
if(rst)
cfg_delay <= 32'd0;
else if( cfg_delay < 32'd3000000)//delay 100ms
cfg_delay <= cfg_delay + 1'b1;
else;
end
//----------------------------------------------
always@(posedge clk_30M or posedge rst)
begin
if(rst)
send_spi_vld <= 1'b0;
else if( (send_spi_vld == 1'b0 && spi_busy == 1'b0) && (cfg_cnt <= 8'd183 && cfg_delay >= 32'd3000000))
send_spi_vld <= 1'b1;
else
send_spi_vld <= 1'b0;
end
//-----------------------------------------------------------
always@(posedge clk_30M or posedge rst)
begin
if(rst)
cfg_cnt <= 8'd0;
else if(cfg_cnt <= 8'd183 && send_spi_vld == 1'b1)
cfg_cnt <= cfg_cnt + 1'b1;
else;
end
//----transmit to 7043----
spi_m #(.WIDTH(24)) i_spi_m (
.clk (clk_30M ),
.rst (rst ),
.din (mem_reg1[cfg_cnt] ),
.din_vld(send_spi_vld ),
.scl (HMC7043_SCLK ), //输出SPI总线时钟信号
.cs_n (HMC7043_SEN ), //输出SPI总线使能信号
.mdo (HMC7043_SDATA ), //输出SPI总线数据信号
.busy (spi_busy )
);
endmodule
二，HMC7044芯片配置
3.2 GHz HMC7044时钟抖动衰减器内置可以支持和增强该接口标准特性的独特功能。HMC7044提供50 fs抖动性能，可改善高速数据转换器的信噪比和动态范围。HMC7044可以器件提供14路低噪声且可配置的输出，可以灵活地与许多不同的器件接口。HMC7044还具有各种时钟管理和分配特性，使得基站设计人员利用单个器件就能构建完整的时钟设计。基站应用中有许多串行JESD204B数据转换器通道需要将其数据帧与FPGA对齐。HMC7044时钟抖动衰减器可在数据转换器系统中产生源同步且可调的样本和帧对齐（SYSREF）时钟，使JESD204B系统设计得以简化。该器件具有两个锁相环（PLL）和重叠的片内压控振荡器（VCO）。
1，HMC7044电路图：
2，HMC7044芯片管脚及其控制信号输出输入脚：
input clk_30M ,
input rst ,
output HMC7044_SEN ,
output HMC7044_SCLK ,
output HMC7044_SDATA ,
output reg HMC7044_RESET = 1'b1 ,
output HMC7044_SYNC ,
output HMC7044_RFSYNC_P ,
output HMC7044_RFSYNC_N ,
input HMC7044_GPIO1 ,//default ,pll locked
input HMC7044_GPIO2 ,//default ,clk phase status
output HMC7044_GPIO3 ,//default ,sleep mode
output HMC7044_GPIO4 //default ,pluse generator request 
第一个PLL将一个低噪声、本地压控时钟振荡器（VCXO）锁定至噪声相对较高的参考，而第二个PLL将VCXO信号倍频至VCO频率，仅增加非常小的噪声。对于蜂窝基础设施JESD204B时钟产生、无线基础设施、数据转换器时钟、微波基带卡和其它高速通信应用，HMC7044架构可提供出色的频率产生性能，相位噪声和积分抖动均很低。
寄存器参数控制：
mem_reg1[0] = 24'h009600 ;
mem_reg1[1] = 24'h009700 ;
mem_reg1[2] = 24'h009800 ;
mem_reg1[3] = 24'h009900 ;
mem_reg1[4] = 24'h009a00 ;
mem_reg1[5] = 24'h009baa ;
mem_reg1[6] = 24'h009caa ;
mem_reg1[7] = 24'h009daa ;
mem_reg1[8] = 24'h009eaa ;
mem_reg1[9] = 24'h009f4d ;
mem_reg1[10] = 24'h00a0df ;
mem_reg1[11] = 24'h00a197 ;
mem_reg1[12] = 24'h00a203 ;
mem_reg1[13] = 24'h00a300 ;
mem_reg1[14] = 24'h00a400 ;
mem_reg1[15] = 24'h00a506 ;
mem_reg1[16] = 24'h00a61c ;
mem_reg1[17] = 24'h00a700 ;
mem_reg1[18] = 24'h00a806 ;
mem_reg1[19] = 24'h00a900 ;
mem_reg1[20] = 24'h00ab00 ;
mem_reg1[21] = 24'h00ac20 ;
mem_reg1[22] = 24'h00ad00 ;
mem_reg1[23] = 24'h00ae08 ;
mem_reg1[24] = 24'h00af50 ;
mem_reg1[25] = 24'h00b004 ;
mem_reg1[26] = 24'h00b10d ;
mem_reg1[27] = 24'h00b200 ;
mem_reg1[28] = 24'h00b300 ;
mem_reg1[29] = 24'h00b400 ;
mem_reg1[30] = 24'h00b500 ;
mem_reg1[31] = 24'h00b600 ;
mem_reg1[32] = 24'h00b700 ;
mem_reg1[33] = 24'h00b800 ;
//global
mem_reg1[34] = 24'h000000;
mem_reg1[35] = 24'h000100;
mem_reg1[36] = 24'h000204;
mem_reg1[37] = 24'h000335;//pll1 enable
mem_reg1[38] = 24'h00047f;//14 channel output enable
mem_reg1[39] = 24'h000553;//clkin0 ,clkin1 enable
mem_reg1[40] = 24'h000600;
mem_reg1[41] = 24'h000700;
mem_reg1[42] = 24'h000901;//off SYNC at lock
//pll2
mem_reg1[43] = 24'h003101;
mem_reg1[44] = 24'h003200; //pll2 ref_div
mem_reg1[45] = 24'h003305; //pll2 R_div
mem_reg1[46] = 24'h003400; //pll2 R_div
mem_reg1[47] = 24'h003560; //pll2 N_div
mem_reg1[48] = 24'h003600; //pll2 N_div
mem_reg1[49] = 24'h00370f;
mem_reg1[50] = 24'h00381e;
mem_reg1[51] = 24'h003901;
mem_reg1[52] = 24'h003a31;
mem_reg1[53] = 24'h003b31;
//pll1
mem_reg1[54] = 24'h000a07;
mem_reg1[55] = 24'h000b07;
mem_reg1[56] = 24'h000c07;
mem_reg1[57] = 24'h000d07;
mem_reg1[58] = 24'h000e07;
mem_reg1[59] = 24'h0014e1;//第一优先级为CLK1
mem_reg1[60] = 24'h001503;//LOS VAL TIME
mem_reg1[61] = 24'h00160f;//holdover exit control
mem_reg1[62] = 24'h001700;
mem_reg1[63] = 24'h001804;
mem_reg1[64] = 24'h001900;
mem_reg1[65] = 24'h001a08;
mem_reg1[66] = 24'h001b18;//PFD UP/DOWN ENABLE
mem_reg1[67] = 24'h001c01;//clkin0 prescaler:1
mem_reg1[68] = 24'h001d01;//clkin1 prescaler:1
mem_reg1[69] = 24'h001e01;//clkin2 prescaler:1
mem_reg1[70] = 24'h001f01;//clkin3 prescaler:1
mem_reg1[71] = 24'h002001;//oscclk prescaler:1
mem_reg1[72] = 24'h002103;//R1 LSB:3
mem_reg1[73] = 24'h002200;//R1 MSB:0
mem_reg1[74] = 24'h002603;//N1 LSB:3
mem_reg1[75] = 24'h002700;//N1 MSB:0
mem_reg1[76] = 24'h00280f;//LCM CYCLES
mem_reg1[77] = 24'h00290D;//Auto Switching
mem_reg1[78] = 24'h002a00;//HoldoffTimer
//sysref
mem_reg1[79] = 24'h005a00;//level control,pluse generator
mem_reg1[80] = 24'h005b06; //SYNC CONTROL
mem_reg1[81] = 24'h005c00;//sysref timer control LSB <= 4MHz
mem_reg1[82] = 24'h005d08;//sysref timer control MSB
mem_reg1[83] = 24'h004600;//GPI1 setting
mem_reg1[84] = 24'h004700;//GPI2 setting
mem_reg1[85] = 24'h004809;//GPI3 setting
mem_reg1[86] = 24'h004911;//GPO4 setting
mem_reg1[87] = 24'h005037;//GPO1 setting
mem_reg1[88] = 24'h005133;//GPO2 setting
mem_reg1[89] = 24'h005200;//GPO3 setting
mem_reg1[90] = 24'h005300;//GPO4 setting
mem_reg1[91] = 24'h005403;//SDATA control
mem_reg1[92] = 24'h006400;//pll2 external vco control
mem_reg1[93] = 24'h006500;//delay low power mode
mem_reg1[94] = 24'h007003;//PLL1 alarm mask
mem_reg1[95] = 24'h007110;//Alarm Mask Control
//clock distribute
mem_reg1[96] = 24'h00c8f3;//ch0 mode,channel enable
mem_reg1[97] = {16'h00c9,CLKOUT0_DIV[7:0]};//ch0 divider lsb [7:0]
mem_reg1[98] = {16'h00ca,4'h0,CLKOUT0_DIV[11:8]};//ch0 divider Msb [11:8]
mem_reg1[99] = 24'h00cb00;//ch0 fine delay step,step size:25ps
mem_reg1[100] = 24'h00cc00;//ch0 coarse digital delay
mem_reg1[101] = 24'h00cd00;//ch0 multislip digital delay,lsb [7:0]
mem_reg1[102] = 24'h00ce00;//ch0 multislip digital delay Msb [11:8]
mem_reg1[103] = 24'h00cf00;//ch0 divider output
mem_reg1[104] = 24'h00d031;//ch0 force mute,nomal,lvds mode
mem_reg1[105] = 24'h00d2f3;//ch1 mode,channel enable
mem_reg1[106] = {16'h00d3,CLKOUT1_DIV[7:0]};//ch1 divider lsb [7:0]
mem_reg1[107] = {16'h00d4,4'h0,CLKOUT1_DIV[11:8]};//ch1 divider Msb [11:8]
mem_reg1[108] = 24'h00d500;//ch1 fine delay step,step size:25ps
mem_reg1[109] = 24'h00d600;//ch1 coarse digital delay
mem_reg1[110] = 24'h00d700;//ch1 multislip digital delay,lsb [7:0]
mem_reg1[111] = 24'h00d800;//ch1 multislip digital delay Msb [11:8]
mem_reg1[112] = 24'h00d900;//ch1 divider output
mem_reg1[113] = 24'h00da31;//ch1 force mute,nomal,lvds mode
mem_reg1[114] = 24'h00dcf3;//ch2 mode,channel enable
mem_reg1[115] = {16'h00dd,CLKOUT2_DIV[7:0]};//ch2 divider lsb [7:0]
mem_reg1[116] = {16'h00de,4'h0,CLKOUT2_DIV[11:8]};//ch2 divider Msb [11:8]
mem_reg1[117] = 24'h00df00;//ch2 fine delay step,step size:25ps
mem_reg1[118] = 24'h00e000;//ch2 coarse digital delay
mem_reg1[119] = 24'h00e100;//ch2 multislip digital delay,lsb [7:0]
mem_reg1[120] = 24'h00e200;//ch2 multislip digital delay Msb [11:8]
mem_reg1[121] = 24'h00e300;//ch2 divider output
mem_reg1[122] = 24'h00e431;//ch2 force mute,nomal,lvds mode
mem_reg1[123] = 24'h00e6f3;//ch3 mode,channel enable
mem_reg1[124] = {16'h00e7,CLKOUT3_DIV[7:0]};//ch1 divider lsb [7:0]
mem_reg1[125] = {16'h00e8,4'h0,CLKOUT3_DIV[11:8]};//ch1 divider Msb [11:8]
mem_reg1[126] = 24'h00e900;//ch3 fine delay step,step size:25ps
mem_reg1[127] = 24'h00ea00;//ch3 coarse digital delay
mem_reg1[128] = 24'h00eb00;//ch3 multislip digital delay,lsb [7:0]
mem_reg1[129] = 24'h00ec00;//ch3 multislip digital delay Msb [11:8]
mem_reg1[130] = 24'h00ed00;//ch3 divider output
mem_reg1[131] = 24'h00ee31;//ch3 force mute,nomal,lvds mode
mem_reg1[132] = 24'h00f0f3;//ch4 mode,channel enable
mem_reg1[133] = {16'h00f1,CLKOUT4_DIV[7:0]};//ch4 divider lsb [7:0]
mem_reg1[134] = {16'h00f2,4'h0,CLKOUT4_DIV[11:8]};//ch4 divider Msb [11:8]
mem_reg1[135] = 24'h00f300;//ch4 fine delay step,step size:25ps
mem_reg1[136] = 24'h00f400;//ch4 coarse digital delay
mem_reg1[137] = 24'h00f500;//ch4 multislip digital delay,lsb [7:0]
mem_reg1[138] = 24'h00f600;//ch4 multislip digital delay Msb [11:8]
mem_reg1[139] = 24'h00f700;//ch4 divider output
mem_reg1[140] = 24'h00f831;//ch4 force mute,nomal,lvds mode
mem_reg1[141] = 24'h00faf3;//ch5 mode,channel enable
mem_reg1[142] = {16'h00fb,CLKOUT5_DIV[7:0]};//ch5 divider lsb [7:0]
mem_reg1[143] = {16'h00fc,4'h0,CLKOUT5_DIV[11:8]};//ch5 divider Msb [11:8]
mem_reg1[144] = 24'h00fd00;//ch5 fine delay step,step size:25ps
mem_reg1[145] = 24'h00fe00;//ch5 coarse digital delay
mem_reg1[146] = 24'h00ff00;//ch5 multislip digital delay,lsb [7:0]
mem_reg1[147] = 24'h010000;//ch5 multislip digital delay Msb [11:8]
mem_reg1[148] = 24'h010100;//ch5 divider output
mem_reg1[149] = 24'h010231;//ch5 force mute,nomal,lvds mode
mem_reg1[150] = 24'h0104f3;//ch6 mode,channel enable
mem_reg1[151] = {16'h0105,CLKOUT6_DIV[7:0]};//ch6 divider lsb [7:0]
mem_reg1[152] = {16'h0106,4'h0,CLKOUT6_DIV[11:8]};//ch6 divider Msb [11:8]
mem_reg1[153] = 24'h010700;//ch6 fine delay step,step size:25ps
mem_reg1[154] = 24'h010800;//ch6 coarse digital delay
mem_reg1[155] = 24'h010900;//ch6 multislip digital delay,lsb [7:0]
mem_reg1[156] = 24'h010a00;//ch6 multislip digital delay Msb [11:8]
mem_reg1[157] = 24'h010b00;//ch6 divider output
mem_reg1[158] = 24'h010c31;//ch6 force mute,nomal,lvds mode
mem_reg1[159] = 24'h010ef3;//ch7 mode,channel enable
mem_reg1[160] = {16'h010f,CLKOUT7_DIV[7:0]};//ch7 divider lsb [7:0]
mem_reg1[161] = {16'h0110,4'h0,CLKOUT7_DIV[11:8]};//ch7 divider Msb [11:8]
mem_reg1[162] = 24'h011100;//ch7 fine delay step,step size:25ps
mem_reg1[163] = 24'h011200;//ch7 coarse digital delay
mem_reg1[164] = 24'h011300;//ch7 multislip digital delay,lsb [7:0]
mem_reg1[165] = 24'h011400;//ch7 multislip digital delay Msb [11:8]
mem_reg1[166] = 24'h011500;//ch7 divider output
mem_reg1[167] = 24'h011631;//ch7 force mute,nomal,lvds mode
mem_reg1[168] = 24'h0118f3;//ch8 mode,channel enable
mem_reg1[169] = {16'h0119,CLKOUT8_DIV[7:0]};//ch8 divider lsb [7:0]
mem_reg1[170] = {16'h011a,4'h0,CLKOUT8_DIV[11:8]};//ch8 divider Msb [11:8]
mem_reg1[171] = 24'h011b00;//ch8 fine delay step,step size:25ps
mem_reg1[172] = 24'h011c00;//ch8 coarse digital delay
mem_reg1[173] = 24'h011d00;//ch8 multislip digital delay,lsb [7:0]
mem_reg1[174] = 24'h011e00;//ch8 multislip digital delay Msb [11:8]
mem_reg1[175] = 24'h011f00;//ch8 divider output
mem_reg1[176] = 24'h012031;//ch8 force mute,nomal,lvds mode
mem_reg1[177] = 24'h0122f3;//ch9 mode,channel enable
mem_reg1[178] = {16'h0123,CLKOUT9_DIV[7:0]};//ch9 divider lsb [7:0]
mem_reg1[179] = {16'h0124,4'h0,CLKOUT9_DIV[11:8]};//ch9 divider Msb [11:8]
mem_reg1[180] = 24'h012500;//ch9 fine delay step,step size:25ps
mem_reg1[181] = 24'h012600;//ch9 coarse digital delay
mem_reg1[182] = 24'h012700;//ch9 multislip digital delay,lsb [7:0]
mem_reg1[183] = 24'h012800;//ch9 multislip digital delay Msb [11:8]
mem_reg1[184] = 24'h012900;//ch9 divider output
mem_reg1[185] = 24'h012a31;//ch9 force mute,nomal,lvds mode
mem_reg1[186] = 24'h012cf3;//ch10 mode,channel enable
mem_reg1[187] = {16'h012d,CLKOUT10_DIV[7:0]};//ch10 divider lsb [7:0]
mem_reg1[188] = {16'h012e,4'h0,CLKOUT10_DIV[11:8]};//ch10 divider Msb [11:8]
mem_reg1[189] = 24'h012f00;//ch10 fine delay step,step size:25ps
mem_reg1[190] = 24'h013000;//ch10 coarse digital delay
mem_reg1[191] = 24'h013100;//ch10 multislip digital delay,lsb [7:0]
mem_reg1[192] = 24'h013200;//ch10 multislip digital delay Msb [11:8]
mem_reg1[193] = 24'h013300;//ch10 divider output
mem_reg1[194] = 24'h013431;//ch10 force mute,nomal,lvds mode
mem_reg1[195] = 24'h0136f3;//ch11 mode,channel enable
mem_reg1[196] = {16'h0137,CLKOUT11_DIV[7:0]};//ch11 divider lsb [7:0]
mem_reg1[197] = {16'h0138,4'h0,CLKOUT11_DIV[11:8]};//ch11 divider Msb [11:8]
mem_reg1[198] = 24'h013900;//ch11 fine delay step,step size:25ps
mem_reg1[199] = 24'h013a00;//ch11 coarse digital delay
mem_reg1[200] = 24'h013b00;//ch11 multislip digital delay,lsb [7:0]
mem_reg1[201] = 24'h013c00;//ch11 multislip digital delay Msb [11:8]
mem_reg1[202] = 24'h013d00;//ch11 divider output
mem_reg1[203] = 24'h013e31;//ch11 force mute,nomal,lvds mode
mem_reg1[204] = 24'h0140f3;//ch12 mode,channel enable
mem_reg1[205] = {16'h0141,CLKOUT12_DIV[7:0]};//ch12 divider lsb [7:0]
mem_reg1[206] = {16'h0142,4'h0,CLKOUT12_DIV[11:8]};//ch12 divider Msb [11:8]
mem_reg1[207] = 24'h014300;//ch12 fine delay step,step size:25ps
mem_reg1[208] = 24'h014400;//ch12 coarse digital delay
mem_reg1[209] = 24'h014500;//ch12 multislip digital delay,lsb [7:0]
mem_reg1[210] = 24'h014600;//ch12 multislip digital delay Msb [11:8]
mem_reg1[211] = 24'h014700;//ch12 divider output
mem_reg1[212] = 24'h014831;//ch12 force mute,nomal,lvds mode
mem_reg1[213] = 24'h014af3;//ch13 mode,channel enable
mem_reg1[214] = {16'h014b,CLKOUT13_DIV[7:0]};//ch13 divider lsb [7:0]
mem_reg1[215] = {16'h014c,4'h0,CLKOUT13_DIV[11:8]};//ch13 divider Msb [11:8]
mem_reg1[216] = 24'h014d00;//ch13 fine delay step,step size:25ps
mem_reg1[217] = 24'h014e00;//ch13 coarse digital delay
mem_reg1[218] = 24'h014f00;//ch13 multislip digital delay,lsb [7:0]
mem_reg1[219] = 24'h015000;//ch13 multislip digital delay Msb [11:8]
mem_reg1[220] = 24'h015100;//ch13 divider output
mem_reg1[221] = 24'h015231;//ch13 force mute,nomal,lvds mode
mem_reg1[222] = 24'h000102;
mem_reg1[223] = 24'h000000;
mem_reg1[224] = 24'h000100; 版权声明：本文为CSDN博主「寒听雪落」的原创文章，遵循CC 4.0 BY-SA版权协议，转载请附上原文出处链接及本声明。
原文链接：https://blog.csdn.net/wangjie36/article/details/121502924
一，HMC7043芯片
MC7043独特的特性是对14个通道分别进行独立灵活的相位管理。所有14个通道均支持频率和相位调整。这些输出还可针对50 Ω或100 Ω内部和外部端接选项进行编程。HMC7043器件具有RF SYNC功能，支持确定性同步多个HMC7043器件，即确保所有时钟输出从同一时钟沿开始。可通过改写嵌套式HMC7043或SYSREF控制单元/分频器，然后重新启动具有新相位的输出分频器来实现。MC7043芯片支持3.2G信号发生。
1，硬件原理图：
（1）HMC7043电路图：
（2）芯片管脚图：
2，芯片读写操作：
（1），读
（2），写
（3），读写时序
（4），寄存器地址参数控制配置
3，控制寄存器映射位描述
4，HMC7043 verilog控制代码
`timescale 1ns / 1ps
// Company:SUBOMB
module HMC7043_CFG #( parameter [11:0] CLKOUT0_DIV = 12'd5 ,
CLKOUT1_DIV = 12'd5 ,
CLKOUT2_DIV = 12'd5 ,
CLKOUT3_DIV = 12'd5 ,
CLKOUT4_DIV = 12'd5 ,
CLKOUT5_DIV = 12'd5 ,
CLKOUT6_DIV = 12'd5 ,
CLKOUT7_DIV = 12'd5 ,
CLKOUT8_DIV = 12'd5 ,
CLKOUT9_DIV = 12'd5 ,
CLKOUT10_DIV = 12'd5 ,
CLKOUT11_DIV = 12'd5 ,
CLKOUT12_DIV = 12'd5 ,
CLKOUT13_DIV = 12'd5
)(
input clk_30M ,
input rst ,
output HMC7043_SEN ,
output HMC7043_SCLK ,
output HMC7043_SDATA ,
output reg HMC7043_RESET = 1'b1 ,
input HMC7043_GPIO //default ,resever
);
// config ad9680 from spi interface//
wire spi_busy ;
reg [7:0] cfg_cnt = 8'd0 ;
reg send_spi_vld = 1'b0 ;
reg [23:0] mem_reg1[22:0] ;
reg [31:0] cfg_delay = 32'd0 ;
//--------------------------------------------------------
initial
begin
// mem_reg1[0] = 24'h001500 ; //anolog input
// mem_reg1[1] = 24'h00160e ; //400 ou
//default
mem_reg1[0] = 24'h009600 ;
mem_reg1[1] = 24'h009700 ;
mem_reg1[2] = 24'h009800 ;
mem_reg1[3] = 24'h009900 ;
mem_reg1[4] = 24'h009a00 ;
mem_reg1[5] = 24'h009baa ;
mem_reg1[6] = 24'h009caa ;
mem_reg1[7] = 24'h009daa ;
mem_reg1[8] = 24'h009eaa ;
mem_reg1[9] = 24'h009f4d ;
mem_reg1[10] = 24'h00a0df ;
mem_reg1[11] = 24'h00a197 ;
mem_reg1[12] = 24'h00a203 ;
mem_reg1[13] = 24'h00a300 ;
mem_reg1[14] = 24'h00a400 ;
mem_reg1[15] = 24'h00a506 ;
mem_reg1[16] = 24'h00a61c ;
mem_reg1[17] = 24'h00a700 ;
mem_reg1[18] = 24'h00a806 ;
mem_reg1[19] = 24'h00a900 ;
mem_reg1[20] = 24'h00ab00 ;
mem_reg1[21] = 24'h00ac20 ;
mem_reg1[22] = 24'h00ad00 ;
mem_reg1[23] = 24'h00ae08 ;
mem_reg1[24] = 24'h00af50 ;
mem_reg1[25] = 24'h00b004 ;
mem_reg1[26] = 24'h00b10d ;
mem_reg1[27] = 24'h00b200 ;
mem_reg1[28] = 24'h00b300 ;
mem_reg1[29] = 24'h00b400 ;
mem_reg1[30] = 24'h00b500 ;
mem_reg1[31] = 24'h00b600 ;
mem_reg1[32] = 24'h00b700 ;
mem_reg1[33] = 24'h00b800 ;
//global
mem_reg1[34] = 24'h000000;
mem_reg1[35] = 24'h000100;
mem_reg1[36] = 24'h000204;
mem_reg1[37] = 24'h000334;//sysref timer enable
mem_reg1[38] = 24'h00047f;//14 channel output enable
mem_reg1[39] = 24'h00050f;//reserved
mem_reg1[40] = 24'h000600;
mem_reg1[41] = 24'h000700;
mem_reg1[42] = 24'h000900;//reserved
//input buffer
mem_reg1[43] = 24'h000a07;
mem_reg1[44] = 24'h000b07;
//sysref
mem_reg1[45] = 24'h005a00;//level control,pluse generator
mem_reg1[46] = 24'h005b04;//SYNC CONTROL
mem_reg1[47] = 24'h005c00;//sysref timer control LSB <= 4MHz
mem_reg1[48] = 24'h005d08;//sysref timer control MSB
mem_reg1[49] = 24'h004600;//GPI1 setting
mem_reg1[50] = 24'h005037;//GPO1 setting
mem_reg1[51] = 24'h005403;//SDATA control
mem_reg1[52] = 24'h006400;//clk input control
mem_reg1[53] = 24'h006500;//delay low power mode
mem_reg1[54] = 24'h007110;//Alarm Mask Control
//clock distribute
mem_reg1[55] = 24'h00c8f3;//ch0 mode,channel enable
mem_reg1[56] = {16'h00c9,CLKOUT0_DIV[7:0]};//ch0 divider lsb [7:0]
mem_reg1[57] = {16'h00ca,4'h0,CLKOUT0_DIV[11:8]};//ch0 divider Msb [11:8]
mem_reg1[58] = 24'h00cb00;//ch0 fine delay step,step size:25ps
mem_reg1[59] = 24'h00cc00;//ch0 coarse digital delay
mem_reg1[60] = 24'h00cd00;//ch0 multislip digital delay,lsb [7:0]
mem_reg1[61] = 24'h00ce00;//ch0 multislip digital delay Msb [11:8]
mem_reg1[62] = 24'h00cf00;//ch0 divider output
mem_reg1[63] = 24'h00d031;//ch0 force mute,nomal,lvds mode
mem_reg1[64] = 24'h00d2f3;//ch1 mode,channel enable
mem_reg1[65] = {16'h00d3,CLKOUT1_DIV[7:0]};//ch1 divider lsb [7:0]
mem_reg1[66] = {16'h00d4,4'h0,CLKOUT1_DIV[11:8]};//ch1 divider Msb [11:8]
mem_reg1[67] = 24'h00d500;//ch1 fine delay step,step size:25ps
mem_reg1[68] = 24'h00d600;//ch1 coarse digital delay
mem_reg1[69] = 24'h00d700;//ch1 multislip digital delay,lsb [7:0]
mem_reg1[70] = 24'h00d800;//ch1 multislip digital delay Msb [11:8]
mem_reg1[71] = 24'h00d900;//ch1 divider output
mem_reg1[72] = 24'h00da31;//ch1 force mute,nomal,lvds mode
mem_reg1[73] = 24'h00dcf3;//ch2 mode,channel enable
mem_reg1[74] = {16'h00dd,CLKOUT2_DIV[7:0]};//ch2 divider lsb [7:0]
mem_reg1[75] = {16'h00de,4'h0,CLKOUT2_DIV[11:8]};//ch2 divider Msb [11:8]
mem_reg1[76] = 24'h00df00;//ch2 fine delay step,step size:25ps
mem_reg1[77] = 24'h00e000;//ch2 coarse digital delay
mem_reg1[78] = 24'h00e100;//ch2 multislip digital delay,lsb [7:0]
mem_reg1[79] = 24'h00e200;//ch2 multislip digital delay Msb [11:8]
mem_reg1[80] = 24'h00e300;//ch2 divider output
mem_reg1[81] = 24'h00e431;//ch2 force mute,nomal,lvds mode
mem_reg1[82] = 24'h00e6f3;//ch3 mode,channel enable
mem_reg1[83] = {16'h00e7,CLKOUT3_DIV[7:0]};//ch1 divider lsb [7:0]
mem_reg1[84] = {16'h00e8,4'h0,CLKOUT3_DIV[11:8]};//ch1 divider Msb [11:8]
mem_reg1[85] = 24'h00e900;//ch3 fine delay step,step size:25ps
mem_reg1[86] = 24'h00ea00;//ch3 coarse digital delay
mem_reg1[87] = 24'h00eb00;//ch3 multislip digital delay,lsb [7:0]
mem_reg1[88] = 24'h00ec00;//ch3 multislip digital delay Msb [11:8]
mem_reg1[89] = 24'h00ed00;//ch3 divider output
mem_reg1[90] = 24'h00ee31;//ch3 force mute,nomal,lvds mode
mem_reg1[91] = 24'h00f0f3;//ch4 mode,channel enable
mem_reg1[92] = {16'h00f1,CLKOUT4_DIV[7:0]};//ch4 divider lsb [7:0]
mem_reg1[93] = {16'h00f2,4'h0,CLKOUT4_DIV[11:8]};//ch4 divider Msb [11:8]
mem_reg1[94] = 24'h00f300;//ch4 fine delay step,step size:25ps
mem_reg1[95] = 24'h00f400;//ch4 coarse digital delay
mem_reg1[96] = 24'h00f500;//ch4 multislip digital delay,lsb [7:0]
mem_reg1[97] = 24'h00f600;//ch4 multislip digital delay Msb [11:8]
mem_reg1[98] = 24'h00f700;//ch4 divider output
mem_reg1[99] = 24'h00f831;//ch4 force mute,nomal,lvds mode
mem_reg1[100] = 24'h00faf3;//ch5 mode,channel enable
mem_reg1[101] = {16'h00fb,CLKOUT5_DIV[7:0]};//ch5 divider lsb [7:0]
mem_reg1[102] = {16'h00fc,4'h0,CLKOUT5_DIV[11:8]};//ch5 divider Msb [11:8]
mem_reg1[103] = 24'h00fd00;//ch5 fine delay step,step size:25ps
mem_reg1[104] = 24'h00fe00;//ch5 coarse digital delay
mem_reg1[105] = 24'h00ff00;//ch5 multislip digital delay,lsb [7:0]
mem_reg1[106] = 24'h010000;//ch5 multislip digital delay Msb [11:8]
mem_reg1[107] = 24'h010100;//ch5 divider output
mem_reg1[108] = 24'h010231;//ch5 force mute,nomal,lvds mode
mem_reg1[109] = 24'h0104f3;//ch6 mode,channel enable
mem_reg1[110] = {16'h0105,CLKOUT6_DIV[7:0]};//ch6 divider lsb [7:0]
mem_reg1[111] = {16'h0106,4'h0,CLKOUT6_DIV[11:8]};//ch6 divider Msb [11:8]
mem_reg1[112] = 24'h010700;//ch6 fine delay step,step size:25ps
mem_reg1[113] = 24'h010800;//ch6 coarse digital delay
mem_reg1[114] = 24'h010900;//ch6 multislip digital delay,lsb [7:0]
mem_reg1[115] = 24'h010a00;//ch6 multislip digital delay Msb [11:8]
mem_reg1[116] = 24'h010b00;//ch6 divider output
mem_reg1[117] = 24'h010c31;//ch6 force mute,nomal,lvds mode
mem_reg1[118] = 24'h010ef3;//ch7 mode,channel enable
mem_reg1[119] = {16'h010f,CLKOUT7_DIV[7:0]};//ch7 divider lsb [7:0]
mem_reg1[120] = {16'h0110,4'h0,CLKOUT7_DIV[11:8]};//ch7 divider Msb [11:8]
mem_reg1[121] = 24'h011100;//ch7 fine delay step,step size:25ps
mem_reg1[122] = 24'h011200;//ch7 coarse digital delay
mem_reg1[123] = 24'h011300;//ch7 multislip digital delay,lsb [7:0]
mem_reg1[124] = 24'h011400;//ch7 multislip digital delay Msb [11:8]
mem_reg1[125] = 24'h011500;//ch7 divider output
mem_reg1[126] = 24'h011631;//ch7 force mute,nomal,lvds mode
mem_reg1[127] = 24'h0118f3;//ch8 mode,channel enable
mem_reg1[128] = {16'h0119,CLKOUT8_DIV[7:0]};//ch8 divider lsb [7:0]
mem_reg1[129] = {16'h011a,4'h0,CLKOUT8_DIV[11:8]};//ch8 divider Msb [11:8]
mem_reg1[130] = 24'h011b00;//ch8 fine delay step,step size:25ps
mem_reg1[131] = 24'h011c00;//ch8 coarse digital delay
mem_reg1[132] = 24'h011d00;//ch8 multislip digital delay,lsb [7:0]
mem_reg1[133] = 24'h011e00;//ch8 multislip digital delay Msb [11:8]
mem_reg1[134] = 24'h011f00;//ch8 divider output
mem_reg1[135] = 24'h012031;//ch8 force mute,nomal,lvds mode
mem_reg1[136] = 24'h0122f3;//ch9 mode,channel enable
mem_reg1[137] = {16'h0123,CLKOUT9_DIV[7:0]};//ch9 divider lsb [7:0]
mem_reg1[138] = {16'h0124,4'h0,CLKOUT9_DIV[11:8]};//ch9 divider Msb [11:8]
mem_reg1[139] = 24'h012500;//ch9 fine delay step,step size:25ps
mem_reg1[140] = 24'h012600;//ch9 coarse digital delay
mem_reg1[141] = 24'h012700;//ch9 multislip digital delay,lsb [7:0]
mem_reg1[142] = 24'h012800;//ch9 multislip digital delay Msb [11:8]
mem_reg1[143] = 24'h012900;//ch9 divider output
mem_reg1[144] = 24'h012a31;//ch9 force mute,nomal,lvds mode
mem_reg1[145] = 24'h012cf3;//ch10 mode,channel enable
mem_reg1[146] = {16'h012d,CLKOUT10_DIV[7:0]};//ch10 divider lsb [7:0]
mem_reg1[147] = {16'h012e,4'h0,CLKOUT10_DIV[11:8]};//ch10 dividerMsb [11:8]
mem_reg1[148] = 24'h012f00;//ch10 fine delay step,step size:25ps
mem_reg1[149] = 24'h013000;//ch10 coarse digital delay
mem_reg1[150] = 24'h013100;//ch10 multislip digital delay,lsb [7:0]
mem_reg1[151] = 24'h013200;//ch10 multislip digital delay Msb [11:8]
mem_reg1[152] = 24'h013300;//ch10 divider output
mem_reg1[153] = 24'h013431;//ch10 force mute,nomal,lvds mode
mem_reg1[154] = 24'h0136f3;//ch11 mode,channel enable
mem_reg1[155] = {16'h0137,CLKOUT11_DIV[7:0]};//ch11 divider lsb [7:0]
mem_reg1[156] = {16'h0138,4'h0,CLKOUT11_DIV[11:8]};//ch11 divider Msb [11:8]
mem_reg1[157] = 24'h013900;//ch11 fine delay step,step size:25ps
mem_reg1[158] = 24'h013a00;//ch11 coarse digital delay
mem_reg1[159] = 24'h013b00;//ch11 multislip digital delay,lsb [7:0]
mem_reg1[160] = 24'h013c00;//ch11 multislip digital delay Msb [11:8]
mem_reg1[161] = 24'h013d00;//ch11 divider output
mem_reg1[162] = 24'h013e31;//ch11 force mute,nomal,lvds mode
mem_reg1[163] = 24'h0140f3;//ch12 mode,channel enable
mem_reg1[164] = {16'h0141,CLKOUT12_DIV[7:0]};//ch12 divider lsb [7:0]
mem_reg1[165] = {16'h0142,4'h0,CLKOUT12_DIV[11:8]};//ch12 divider Msb [11:8]
mem_reg1[166] = 24'h014300;//ch12 fine delay step,step size:25ps
mem_reg1[167] = 24'h014400;//ch12 coarse digital delay
mem_reg1[168] = 24'h014500;//ch12 multislip digital delay,lsb [7:0]
mem_reg1[169] = 24'h014600;//ch12 multislip digital delay Msb [11:8]
mem_reg1[170] = 24'h014700;//ch12 divider output
mem_reg1[171] = 24'h014831;//ch12 force mute,nomal,lvds mode
mem_reg1[172] = 24'h014af3;//ch13 mode,channel enable
mem_reg1[173] = {16'h014b,CLKOUT13_DIV[7:0]};//ch13 divider lsb [7:0]
mem_reg1[174] = {16'h014c,4'h0,CLKOUT13_DIV[11:8]};//ch13 divider Msb [11:8]
mem_reg1[175] = 24'h014d00;//ch13 fine delay step,step size:25ps
mem_reg1[176] = 24'h014e00;//ch13 coarse digital delay
mem_reg1[177] = 24'h014f00;//ch13 multislip digital delay,lsb [7:0]
mem_reg1[178] = 24'h015000;//ch13 multislip digital delay Msb [11:8]
mem_reg1[179] = 24'h015100;//ch13 divider output
mem_reg1[180] = 24'h015231;//ch13 force mute,nomal,lvds mode
mem_reg1[181] = 24'h000102;
mem_reg1[182] = 24'h000000;
mem_reg1[183] = 24'h000100;
end
//----------------------------------------------
always@(posedge clk_30M or posedge rst)
begin
if(rst)
cfg_delay <= 32'd0;
else if( cfg_delay < 32'd3000000)//delay 100ms
cfg_delay <= cfg_delay + 1'b1;
else;
end
//----------------------------------------------
always@(posedge clk_30M or posedge rst)
begin
if(rst)
send_spi_vld <= 1'b0;
else if( (send_spi_vld == 1'b0 && spi_busy == 1'b0) && (cfg_cnt <= 8'd183 && cfg_delay >= 32'd3000000))
send_spi_vld <= 1'b1;
else
send_spi_vld <= 1'b0;
end
//-----------------------------------------------------------
always@(posedge clk_30M or posedge rst)
begin
if(rst)
cfg_cnt <= 8'd0;
else if(cfg_cnt <= 8'd183 && send_spi_vld == 1'b1)
cfg_cnt <= cfg_cnt + 1'b1;
else;
end
//----transmit to 7043----
spi_m #(.WIDTH(24)) i_spi_m (
.clk (clk_30M ),
.rst (rst ),
.din (mem_reg1[cfg_cnt] ),
.din_vld(send_spi_vld ),
.scl (HMC7043_SCLK ), //输出SPI总线时钟信号
.cs_n (HMC7043_SEN ), //输出SPI总线使能信号
.mdo (HMC7043_SDATA ), //输出SPI总线数据信号
.busy (spi_busy )
);
endmodule
二，HMC7044芯片配置
3.2 GHz HMC7044时钟抖动衰减器内置可以支持和增强该接口标准特性的独特功能。HMC7044提供50 fs抖动性能，可改善高速数据转换器的信噪比和动态范围。HMC7044可以器件提供14路低噪声且可配置的输出，可以灵活地与许多不同的器件接口。HMC7044还具有各种时钟管理和分配特性，使得基站设计人员利用单个器件就能构建完整的时钟设计。基站应用中有许多串行JESD204B数据转换器通道需要将其数据帧与FPGA对齐。HMC7044时钟抖动衰减器可在数据转换器系统中产生源同步且可调的样本和帧对齐（SYSREF）时钟，使JESD204B系统设计得以简化。该器件具有两个锁相环（PLL）和重叠的片内压控振荡器（VCO）。
1，HMC7044电路图：
2，HMC7044芯片管脚及其控制信号输出输入脚：
input clk_30M ,
input rst ,
output HMC7044_SEN ,
output HMC7044_SCLK ,
output HMC7044_SDATA ,
output reg HMC7044_RESET = 1'b1 ,
output HMC7044_SYNC ,
output HMC7044_RFSYNC_P ,
output HMC7044_RFSYNC_N ,
input HMC7044_GPIO1 ,//default ,pll locked
input HMC7044_GPIO2 ,//default ,clk phase status
output HMC7044_GPIO3 ,//default ,sleep mode
output HMC7044_GPIO4 //default ,pluse generator request 
第一个PLL将一个低噪声、本地压控时钟振荡器（VCXO）锁定至噪声相对较高的参考，而第二个PLL将VCXO信号倍频至VCO频率，仅增加非常小的噪声。对于蜂窝基础设施JESD204B时钟产生、无线基础设施、数据转换器时钟、微波基带卡和其它高速通信应用，HMC7044架构可提供出色的频率产生性能，相位噪声和积分抖动均很低。
寄存器参数控制：
mem_reg1[0] = 24'h009600 ;
mem_reg1[1] = 24'h009700 ;
mem_reg1[2] = 24'h009800 ;
mem_reg1[3] = 24'h009900 ;
mem_reg1[4] = 24'h009a00 ;
mem_reg1[5] = 24'h009baa ;
mem_reg1[6] = 24'h009caa ;
mem_reg1[7] = 24'h009daa ;
mem_reg1[8] = 24'h009eaa ;
mem_reg1[9] = 24'h009f4d ;
mem_reg1[10] = 24'h00a0df ;
mem_reg1[11] = 24'h00a197 ;
mem_reg1[12] = 24'h00a203 ;
mem_reg1[13] = 24'h00a300 ;
mem_reg1[14] = 24'h00a400 ;
mem_reg1[15] = 24'h00a506 ;
mem_reg1[16] = 24'h00a61c ;
mem_reg1[17] = 24'h00a700 ;
mem_reg1[18] = 24'h00a806 ;
mem_reg1[19] = 24'h00a900 ;
mem_reg1[20] = 24'h00ab00 ;
mem_reg1[21] = 24'h00ac20 ;
mem_reg1[22] = 24'h00ad00 ;
mem_reg1[23] = 24'h00ae08 ;
mem_reg1[24] = 24'h00af50 ;
mem_reg1[25] = 24'h00b004 ;
mem_reg1[26] = 24'h00b10d ;
mem_reg1[27] = 24'h00b200 ;
mem_reg1[28] = 24'h00b300 ;
mem_reg1[29] = 24'h00b400 ;
mem_reg1[30] = 24'h00b500 ;
mem_reg1[31] = 24'h00b600 ;
mem_reg1[32] = 24'h00b700 ;
mem_reg1[33] = 24'h00b800 ;
//global
mem_reg1[34] = 24'h000000;
mem_reg1[35] = 24'h000100;
mem_reg1[36] = 24'h000204;
mem_reg1[37] = 24'h000335;//pll1 enable
mem_reg1[38] = 24'h00047f;//14 channel output enable
mem_reg1[39] = 24'h000553;//clkin0 ,clkin1 enable
mem_reg1[40] = 24'h000600;
mem_reg1[41] = 24'h000700;
mem_reg1[42] = 24'h000901;//off SYNC at lock
//pll2
mem_reg1[43] = 24'h003101;
mem_reg1[44] = 24'h003200; //pll2 ref_div
mem_reg1[45] = 24'h003305; //pll2 R_div
mem_reg1[46] = 24'h003400; //pll2 R_div
mem_reg1[47] = 24'h003560; //pll2 N_div
mem_reg1[48] = 24'h003600; //pll2 N_div
mem_reg1[49] = 24'h00370f;
mem_reg1[50] = 24'h00381e;
mem_reg1[51] = 24'h003901;
mem_reg1[52] = 24'h003a31;
mem_reg1[53] = 24'h003b31;
//pll1
mem_reg1[54] = 24'h000a07;
mem_reg1[55] = 24'h000b07;
mem_reg1[56] = 24'h000c07;
mem_reg1[57] = 24'h000d07;
mem_reg1[58] = 24'h000e07;
mem_reg1[59] = 24'h0014e1;//第一优先级为CLK1
mem_reg1[60] = 24'h001503;//LOS VAL TIME
mem_reg1[61] = 24'h00160f;//holdover exit control
mem_reg1[62] = 24'h001700;
mem_reg1[63] = 24'h001804;
mem_reg1[64] = 24'h001900;
mem_reg1[65] = 24'h001a08;
mem_reg1[66] = 24'h001b18;//PFD UP/DOWN ENABLE
mem_reg1[67] = 24'h001c01;//clkin0 prescaler:1
mem_reg1[68] = 24'h001d01;//clkin1 prescaler:1
mem_reg1[69] = 24'h001e01;//clkin2 prescaler:1
mem_reg1[70] = 24'h001f01;//clkin3 prescaler:1
mem_reg1[71] = 24'h002001;//oscclk prescaler:1
mem_reg1[72] = 24'h002103;//R1 LSB:3
mem_reg1[73] = 24'h002200;//R1 MSB:0
mem_reg1[74] = 24'h002603;//N1 LSB:3
mem_reg1[75] = 24'h002700;//N1 MSB:0
mem_reg1[76] = 24'h00280f;//LCM CYCLES
mem_reg1[77] = 24'h00290D;//Auto Switching
mem_reg1[78] = 24'h002a00;//HoldoffTimer
//sysref
mem_reg1[79] = 24'h005a00;//level control,pluse generator
mem_reg1[80] = 24'h005b06; //SYNC CONTROL
mem_reg1[81] = 24'h005c00;//sysref timer control LSB <= 4MHz
mem_reg1[82] = 24'h005d08;//sysref timer control MSB
mem_reg1[83] = 24'h004600;//GPI1 setting
mem_reg1[84] = 24'h004700;//GPI2 setting
mem_reg1[85] = 24'h004809;//GPI3 setting
mem_reg1[86] = 24'h004911;//GPO4 setting
mem_reg1[87] = 24'h005037;//GPO1 setting
mem_reg1[88] = 24'h005133;//GPO2 setting
mem_reg1[89] = 24'h005200;//GPO3 setting
mem_reg1[90] = 24'h005300;//GPO4 setting
mem_reg1[91] = 24'h005403;//SDATA control
mem_reg1[92] = 24'h006400;//pll2 external vco control
mem_reg1[93] = 24'h006500;//delay low power mode
mem_reg1[94] = 24'h007003;//PLL1 alarm mask
mem_reg1[95] = 24'h007110;//Alarm Mask Control
//clock distribute
mem_reg1[96] = 24'h00c8f3;//ch0 mode,channel enable
mem_reg1[97] = {16'h00c9,CLKOUT0_DIV[7:0]};//ch0 divider lsb [7:0]
mem_reg1[98] = {16'h00ca,4'h0,CLKOUT0_DIV[11:8]};//ch0 divider Msb [11:8]
mem_reg1[99] = 24'h00cb00;//ch0 fine delay step,step size:25ps
mem_reg1[100] = 24'h00cc00;//ch0 coarse digital delay
mem_reg1[101] = 24'h00cd00;//ch0 multislip digital delay,lsb [7:0]
mem_reg1[102] = 24'h00ce00;//ch0 multislip digital delay Msb [11:8]
mem_reg1[103] = 24'h00cf00;//ch0 divider output
mem_reg1[104] = 24'h00d031;//ch0 force mute,nomal,lvds mode
mem_reg1[105] = 24'h00d2f3;//ch1 mode,channel enable
mem_reg1[106] = {16'h00d3,CLKOUT1_DIV[7:0]};//ch1 divider lsb [7:0]
mem_reg1[107] = {16'h00d4,4'h0,CLKOUT1_DIV[11:8]};//ch1 divider Msb [11:8]
mem_reg1[108] = 24'h00d500;//ch1 fine delay step,step size:25ps
mem_reg1[109] = 24'h00d600;//ch1 coarse digital delay
mem_reg1[110] = 24'h00d700;//ch1 multislip digital delay,lsb [7:0]
mem_reg1[111] = 24'h00d800;//ch1 multislip digital delay Msb [11:8]
mem_reg1[112] = 24'h00d900;//ch1 divider output
mem_reg1[113] = 24'h00da31;//ch1 force mute,nomal,lvds mode
mem_reg1[114] = 24'h00dcf3;//ch2 mode,channel enable
mem_reg1[115] = {16'h00dd,CLKOUT2_DIV[7:0]};//ch2 divider lsb [7:0]
mem_reg1[116] = {16'h00de,4'h0,CLKOUT2_DIV[11:8]};//ch2 divider Msb [11:8]
mem_reg1[117] = 24'h00df00;//ch2 fine delay step,step size:25ps
mem_reg1[118] = 24'h00e000;//ch2 coarse digital delay
mem_reg1[119] = 24'h00e100;//ch2 multislip digital delay,lsb [7:0]
mem_reg1[120] = 24'h00e200;//ch2 multislip digital delay Msb [11:8]
mem_reg1[121] = 24'h00e300;//ch2 divider output
mem_reg1[122] = 24'h00e431;//ch2 force mute,nomal,lvds mode
mem_reg1[123] = 24'h00e6f3;//ch3 mode,channel enable
mem_reg1[124] = {16'h00e7,CLKOUT3_DIV[7:0]};//ch1 divider lsb [7:0]
mem_reg1[125] = {16'h00e8,4'h0,CLKOUT3_DIV[11:8]};//ch1 divider Msb [11:8]
mem_reg1[126] = 24'h00e900;//ch3 fine delay step,step size:25ps
mem_reg1[127] = 24'h00ea00;//ch3 coarse digital delay
mem_reg1[128] = 24'h00eb00;//ch3 multislip digital delay,lsb [7:0]
mem_reg1[129] = 24'h00ec00;//ch3 multislip digital delay Msb [11:8]
mem_reg1[130] = 24'h00ed00;//ch3 divider output
mem_reg1[131] = 24'h00ee31;//ch3 force mute,nomal,lvds mode
mem_reg1[132] = 24'h00f0f3;//ch4 mode,channel enable
mem_reg1[133] = {16'h00f1,CLKOUT4_DIV[7:0]};//ch4 divider lsb [7:0]
mem_reg1[134] = {16'h00f2,4'h0,CLKOUT4_DIV[11:8]};//ch4 divider Msb [11:8]
mem_reg1[135] = 24'h00f300;//ch4 fine delay step,step size:25ps
mem_reg1[136] = 24'h00f400;//ch4 coarse digital delay
mem_reg1[137] = 24'h00f500;//ch4 multislip digital delay,lsb [7:0]
mem_reg1[138] = 24'h00f600;//ch4 multislip digital delay Msb [11:8]
mem_reg1[139] = 24'h00f700;//ch4 divider output
mem_reg1[140] = 24'h00f831;//ch4 force mute,nomal,lvds mode
mem_reg1[141] = 24'h00faf3;//ch5 mode,channel enable
mem_reg1[142] = {16'h00fb,CLKOUT5_DIV[7:0]};//ch5 divider lsb [7:0]
mem_reg1[143] = {16'h00fc,4'h0,CLKOUT5_DIV[11:8]};//ch5 divider Msb [11:8]
mem_reg1[144] = 24'h00fd00;//ch5 fine delay step,step size:25ps
mem_reg1[145] = 24'h00fe00;//ch5 coarse digital delay
mem_reg1[146] = 24'h00ff00;//ch5 multislip digital delay,lsb [7:0]
mem_reg1[147] = 24'h010000;//ch5 multislip digital delay Msb [11:8]
mem_reg1[148] = 24'h010100;//ch5 divider output
mem_reg1[149] = 24'h010231;//ch5 force mute,nomal,lvds mode
mem_reg1[150] = 24'h0104f3;//ch6 mode,channel enable
mem_reg1[151] = {16'h0105,CLKOUT6_DIV[7:0]};//ch6 divider lsb [7:0]
mem_reg1[152] = {16'h0106,4'h0,CLKOUT6_DIV[11:8]};//ch6 divider Msb [11:8]
mem_reg1[153] = 24'h010700;//ch6 fine delay step,step size:25ps
mem_reg1[154] = 24'h010800;//ch6 coarse digital delay
mem_reg1[155] = 24'h010900;//ch6 multislip digital delay,lsb [7:0]
mem_reg1[156] = 24'h010a00;//ch6 multislip digital delay Msb [11:8]
mem_reg1[157] = 24'h010b00;//ch6 divider output
mem_reg1[158] = 24'h010c31;//ch6 force mute,nomal,lvds mode
mem_reg1[159] = 24'h010ef3;//ch7 mode,channel enable
mem_reg1[160] = {16'h010f,CLKOUT7_DIV[7:0]};//ch7 divider lsb [7:0]
mem_reg1[161] = {16'h0110,4'h0,CLKOUT7_DIV[11:8]};//ch7 divider Msb [11:8]
mem_reg1[162] = 24'h011100;//ch7 fine delay step,step size:25ps
mem_reg1[163] = 24'h011200;//ch7 coarse digital delay
mem_reg1[164] = 24'h011300;//ch7 multislip digital delay,lsb [7:0]
mem_reg1[165] = 24'h011400;//ch7 multislip digital delay Msb [11:8]
mem_reg1[166] = 24'h011500;//ch7 divider output
mem_reg1[167] = 24'h011631;//ch7 force mute,nomal,lvds mode
mem_reg1[168] = 24'h0118f3;//ch8 mode,channel enable
mem_reg1[169] = {16'h0119,CLKOUT8_DIV[7:0]};//ch8 divider lsb [7:0]
mem_reg1[170] = {16'h011a,4'h0,CLKOUT8_DIV[11:8]};//ch8 divider Msb [11:8]
mem_reg1[171] = 24'h011b00;//ch8 fine delay step,step size:25ps
mem_reg1[172] = 24'h011c00;//ch8 coarse digital delay
mem_reg1[173] = 24'h011d00;//ch8 multislip digital delay,lsb [7:0]
mem_reg1[174] = 24'h011e00;//ch8 multislip digital delay Msb [11:8]
mem_reg1[175] = 24'h011f00;//ch8 divider output
mem_reg1[176] = 24'h012031;//ch8 force mute,nomal,lvds mode
mem_reg1[177] = 24'h0122f3;//ch9 mode,channel enable
mem_reg1[178] = {16'h0123,CLKOUT9_DIV[7:0]};//ch9 divider lsb [7:0]
mem_reg1[179] = {16'h0124,4'h0,CLKOUT9_DIV[11:8]};//ch9 divider Msb [11:8]
mem_reg1[180] = 24'h012500;//ch9 fine delay step,step size:25ps
mem_reg1[181] = 24'h012600;//ch9 coarse digital delay
mem_reg1[182] = 24'h012700;//ch9 multislip digital delay,lsb [7:0]
mem_reg1[183] = 24'h012800;//ch9 multislip digital delay Msb [11:8]
mem_reg1[184] = 24'h012900;//ch9 divider output
mem_reg1[185] = 24'h012a31;//ch9 force mute,nomal,lvds mode
mem_reg1[186] = 24'h012cf3;//ch10 mode,channel enable
mem_reg1[187] = {16'h012d,CLKOUT10_DIV[7:0]};//ch10 divider lsb [7:0]
mem_reg1[188] = {16'h012e,4'h0,CLKOUT10_DIV[11:8]};//ch10 divider Msb [11:8]
mem_reg1[189] = 24'h012f00;//ch10 fine delay step,step size:25ps
mem_reg1[190] = 24'h013000;//ch10 coarse digital delay
mem_reg1[191] = 24'h013100;//ch10 multislip digital delay,lsb [7:0]
mem_reg1[192] = 24'h013200;//ch10 multislip digital delay Msb [11:8]
mem_reg1[193] = 24'h013300;//ch10 divider output
mem_reg1[194] = 24'h013431;//ch10 force mute,nomal,lvds mode
mem_reg1[195] = 24'h0136f3;//ch11 mode,channel enable
mem_reg1[196] = {16'h0137,CLKOUT11_DIV[7:0]};//ch11 divider lsb [7:0]
mem_reg1[197] = {16'h0138,4'h0,CLKOUT11_DIV[11:8]};//ch11 divider Msb [11:8]
mem_reg1[198] = 24'h013900;//ch11 fine delay step,step size:25ps
mem_reg1[199] = 24'h013a00;//ch11 coarse digital delay
mem_reg1[200] = 24'h013b00;//ch11 multislip digital delay,lsb [7:0]
mem_reg1[201] = 24'h013c00;//ch11 multislip digital delay Msb [11:8]
mem_reg1[202] = 24'h013d00;//ch11 divider output
mem_reg1[203] = 24'h013e31;//ch11 force mute,nomal,lvds mode
mem_reg1[204] = 24'h0140f3;//ch12 mode,channel enable
mem_reg1[205] = {16'h0141,CLKOUT12_DIV[7:0]};//ch12 divider lsb [7:0]
mem_reg1[206] = {16'h0142,4'h0,CLKOUT12_DIV[11:8]};//ch12 divider Msb [11:8]
mem_reg1[207] = 24'h014300;//ch12 fine delay step,step size:25ps
mem_reg1[208] = 24'h014400;//ch12 coarse digital delay
mem_reg1[209] = 24'h014500;//ch12 multislip digital delay,lsb [7:0]
mem_reg1[210] = 24'h014600;//ch12 multislip digital delay Msb [11:8]
mem_reg1[211] = 24'h014700;//ch12 divider output
mem_reg1[212] = 24'h014831;//ch12 force mute,nomal,lvds mode
mem_reg1[213] = 24'h014af3;//ch13 mode,channel enable
mem_reg1[214] = {16'h014b,CLKOUT13_DIV[7:0]};//ch13 divider lsb [7:0]
mem_reg1[215] = {16'h014c,4'h0,CLKOUT13_DIV[11:8]};//ch13 divider Msb [11:8]
mem_reg1[216] = 24'h014d00;//ch13 fine delay step,step size:25ps
mem_reg1[217] = 24'h014e00;//ch13 coarse digital delay
mem_reg1[218] = 24'h014f00;//ch13 multislip digital delay,lsb [7:0]
mem_reg1[219] = 24'h015000;//ch13 multislip digital delay Msb [11:8]
mem_reg1[220] = 24'h015100;//ch13 divider output
mem_reg1[221] = 24'h015231;//ch13 force mute,nomal,lvds mode
mem_reg1[222] = 24'h000102;
mem_reg1[223] = 24'h000000;
mem_reg1[224] = 24'h000100; 版权声明：本文为CSDN博主「寒听雪落」的原创文章，遵循CC 4.0 BY-SA版权协议，转载请附上原文出处链接及本声明。
原文链接：https://blog.csdn.net/wangjie36/article/details/121502924
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