文章目录[隐藏]

Steps to create BSP, FSBL application and Test application.

ug1271 记录需要全看
看目录时钟主要由时钟芯片产生ug，zcu111的提供gui控制，
scui说明是xtp517 板设置说明是xtp518
zcu111系统控制需要，1串口驱动 2scui主机应用
3使用microUSB连接串口 4重启开发板 5启动scui
scui gui展示在page82
管脚约束 mio分配板配置（条线开关）通过qspi配置rfsoc
板上所有器件管脚接口 FMCP连接

Vivado Design Suite User Guide: Using Constraints (UG903)
ug903 page7 提供xdc文件的获取方法
IMPORTANT: See ZCU111 board documentation for the XDC file.

扩展板HW_FMC_XM500 中 2DAC 2ADC连接高通巴伦 2DAC 2ADC连接低通巴伦
4DAC 4ADC连接通用巴伦

文档末尾由可用文档参考入口
https://www.xilinx.com/support.html xilinx支持
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ug1287 需要全看
dac adc数据通路，各种协议
可通过电脑GUI（ug1309）控制dac ADC的配置，可以测试
主机通过网口与PS通信，PL PS分别有DDR4（page5）
PL PS部分主要模块（page14）
dma 和dac之间需要axi stream(fifo)转换时钟域
Control Switch控制数据来自ddr或者bram,来自ddr就通过fifo输出
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xtp518 设置板卡，主要是开关跳线设置安装方法
要设置正确

串口三个第一个用于arm processor 第二个 pl（microblaze）第三个系统控制
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UG1271 记录需要全看
PL DDR4 16*4=64bit 焊接的；PS DDR4 64bit SODIMM直插式
XCZU28DR-2E, FFVG1517 package
page8 有mio的分配
PS 内存在bank504，PL 在bank67,68,69， page26 有MIO的映射
/SI570 时钟芯片10–810M默认300M，I2C可编程；另一个默认156.250M
时钟结构 page54
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UG1085 全看

查 RF data converter IP 的使用
https://forums.xilinx.com/t5/%E5%85%B6%E4%BB%96IP%E5%BA%94%E7%94%A8/zynq-RFSoC-%E7%9A%84rf-data-converter-IP%E4%BD%BF%E7%94%A8%E8%AF%B7%E6%95%99/m-p/991307
详细参考PG269
ADC的数据是根据AXI总线协议转换后，通过AXI-STREAM数据接口进行输入或输出。
而AXI-LITE也是依据AXI总线协议，以及你设计中IP的baseaddress来进行访问。
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https://forums.xilinx.com/t5/%E5%85%B6%E4%BB%96IP%E5%BA%94%E7%94%A8/RF-data-converter-%E6%98%AF%E5%90%A6%E6%9C%89PS%E6%8E%A7%E5%88%B6RFDC%E7%9A%84%E4%BE%8B%E7%A8%8B%E4%BE%9B%E5%8F%82%E8%80%83/td-p/1065337
你可以在sdk或者vitis的以下路径找到example
C:\Xilinx\Vitis\2019.2\data\embeddedsw\XilinxProcessorIPLib\drivers\rfdc_v7_0\examples
有例程。
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pg269
每个tile一个datapath 一个时钟结构；
IQ需要2adc,adc采回数据12bit精度，在进入下变频前对齐到16bit的高位。
[BD 41-1356] Address block </processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM> is not mapped into </axi_dma_0/Data_S2MM>. Please use Address Editor to either map or exclude it.
ADC采样时钟可以直供或者pll。dac14bit对齐16bit数据的高位。

P38 拥有ADC具有DSP功能阈值检测、正交调制矫正、DDC
偶数编号的rf - adc总是用于I数据路径，奇数编号的rf - adc用于Q数据路径

AD的抽取滤波器，一个是2*，最多三个8*;输出数据是IQ的话，偶尔对应I，奇数对应Q；
DA中偶尔对应I，奇数对应Q；
DA的混合模式可以增强第二奈奎斯特功率，而降低第一奈奎斯特功率。
DA数据最大宽度为256bit，AD为128。输入数据是IQ的话，偶尔对应I，奇数对应Q；

P119 数据格式。

Calibration Mode:Mode 1 is optimal for input frequencies Fsamp/2(Nyquist) +/-
10%. Otherwise, use Mode 2.
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关于DMA的代码基于zed
main
dma初始化。由ID查找现有配置，作为使用的配置，配置初始化，返回成功，
确认是否是sg模式。
系统初始化。先查找配置，作为使用的配置，配置初始化，返回成功。
使能硬件中断。
注册DMA收发中断。
Xil_DCacheFlushRange函数把数据刷新到Dcache到ddr
用到的头文件，
#include “dma_intr.h” ，包含#include “xaxidma.h” #include “xparameters.h” #include “xil_exception.h”
#include “xdebug.h” #include “xscugic.h”
#include “sys_intr.h” ，包含#include “xparameters.h” #include “xil_exception.h” #include “xdebug.h”
#include “xscugic.h”
版本2

版本ZCU111
官方例程，例程1是最简单的测试，例程2是sg模式的中断模式，例程3是sg模式的poll模式，
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tx_rfdc工程
rfdcIP使用一个DA,tile228 dac0,

03版本，为了匹配位宽，设置采样率0.5g，位宽就是32bit，数据时钟为250M

启动

Did you stored a valid Zynq UltraScale+ RFSoC boot image file on to an SD card (and then plug
the SD card into ZCU111 board socket J100)? The valid images are there in rdf0476-zcu111-rf-dc-eval-tool-2019-1.zip

I am suspecting this is related to interface FIFO overflow
The data rate through the interface gearbox FIFOs must be constant during runtime of the RFADC tile,
with no frequency drift between the PL clock and RF-ADC sample clock domains.
If there is a frequency mismatch between these domains, a FIFO overflow might occur.
To have Sampling clock and PL clock be frequency match ,
AXI4-Stream clock must be derived from the same master clock source as the sampling and/or reference clocks to the RF-ADC.
In the system clocking tab, set the clock out for ADC224 as 125 MHz and use the MMCM to derive 250MHz as above.
Or if you have DAC enabled with same sampling rate of 2GSPS , you can have 250MHz clockout.

如果没有通过sd卡启动evaluation design，而是jtag启动的话，那么04208是要配置的。
你看看板子有一堆sma接口的地方有四个在板子边沿的led灯。如果没亮，那就是没有配置。
可以用scui来配置，我们官网有下载

这么做也是可以的。不过bram的接口和axi stream的接口之间还需要转换一下。
这个需要用rtl来实现，自己写好一些封装成IP放到block design中。
转换也很简单，你根据你的rfsoc的stream接口时钟，再看看一个stream多少个16bit sample，
rom一个时钟出32位数据，地址线就累加，输出和输入的数据量对齐就行了。
第二个问题，可以的，axi4-lite的时钟还是要提供的。最好建一个简单的application，读一下ip status。确保时钟等没有问题。

DAC source module is used for feeding the data to DAC.

You can add the processor yourself and please be noted that dac1_axi_clk is DAC’s fabric clock and
it shoul d be driven by the same clock source from DAC reference clock.
So I recommend you use the clock output from RFSoC IP “clk_dac1” to drive this clock.

Steps to create BSP, FSBL application and Test application.

Creating the BSP:

File > New > Board Support Package.
Click on ‘Specify’ and Browse the design file(hdf) contains rfdc IP and Click ‘Finish’.
Rename the Project name (if required) and Click ‘Finish’.
Select the Libmetal library in the Supported Libraries (Libmetal library is required to compile rfdc driver) and Click ‘OK’.

Creating the FSBL:

File > New > Application Project
Give some Project name.
Under Board Support Package select Use existing and select the existing bsp in the drop down list.
Click ‘Next’, select the ZynqMP FSBL and Click ‘Finish’.

Creating the Application:

File > New > Application Project
Give some Project name.
Under Board Support Package select Use existing and select the existing bsp in the drop down list.
Click ‘Next’, select the Empty Application and Click ‘Finish’.
Copy the test application in the src directory of the application project to create the binary file(.elf)

/
/** \page example Examples
You can refer to the below stated example applications for more details on how to use rfdc driver.

@section ex1 xrfdc_selftest_example.c
contains a selftest example for using the rfdc hardware and
RFSoC Data Converter driver.
This example does some writes to the hardware to do some sanity checks
and does a reset to restore the original settings.

For details, see xrfdc_selftest_example.c.

@section ex2 xrfdc_read_write_example.c
Contains an example to use multiple driver “set” APIs to configure the targeted
AMS block.
Subsequently it uses “get” APIs to read back the configurations to ensure
that the desired configurations are applied.
For DAC it sets the following configurations:
MixerSettings, QMCSettings, Write Fabricrate, Decoder mode, Output Current
and Coarse Delay.
For ADC it sets the following configurations:
MixerSettings, QMCSettings, Read Fabricrate and Threshold Settings.
This example shows how to change the configurations for ADC
and DAC using driver functions.
NOTE: The purpose of the example is to show how to use the driver APIs.
For real user scenarios this example will not be relevant.

For details, see xrfdc_read_write_example.c.

@section ex3 xrfdc_intr_example.c
Contains an example to show the interrupts, interrupts are mostly used for error
reporting.
The interrupts do not do any data processing. Since they dont do any data
processing, interrupts are invoked in rare conditions.
The example here attempts to demonstrate users how an error interrupt can be
generated. Also once generated how does the processing happen.
Upon an interrupt, the control reaches to ScuGIC interrupt handler.
From there the control is transferred to the libmetal isr handling which
then calls the driver interrupt handler. Users are expected to register
their callbacks with the driver interrupt framework.
The actual interrupt handling is expected to happen in the user provided
callback.
This example generates ADC fabric interrupts by writing some incorrect
fabric data rate based on the read/write clocks.

For details, see xrfdc_intr_example.c.
*/

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缩写
analog and mixed signal (AMS)
built-in self-test (BIST)
pushbutton (PB)
Memory Interface Generator (MIG)
application processor unit (APU)
Scatter Gather (SG) mode
symmetric multiprocessing(SMP)Linux mode
Quadrature modulation correction (QMC)
Contiguous memory allocator (CMA)
ARM trusted firmware (ATF)
RF Data Converter (RFDC)
Scatter Gather (SG) DMA
super sample rate(SSR)filters
analog and mixed signal (AMS) clocking structure
multi-tile synchronization (MTS) mode
transmission control protocol (TCP) socket
platform management unit (PMU)
power-on reset (POR)
configuration security unit (CSU)
on-chip memory (OCM)
ARM trusted firmware (ATF)
/
power-on reset (POR)
secure digital input/output (SDIO)
Standard Microsystems Corporation (SMSC)
on-the-go (OTG) mode
Gigabit Ethernet MAC (GEM)
FPGA mezzanine card (FMC)
single-pole single-throw (SPST)
Per tile current-mode logic (CML) clock input buffer
Targeted Reference Design