高通智能座舱芯片规格参数（SA6155P/SA8155P/SA8195P）

Feature set		Example use case	Snapdragon™ Auto 6155	Snapdragon Auto 8155	Snapdragon Auto 8195
Process node			11 nm	7 nm	7 nm
CPU type	Cores and frequency	Number and core frequency	Octa core Qualcomm® Kryo™ 460 with ECC 2x gold – 1.9008 GHz 6x silver – 1.5936 GHz	Octa core Kryo 485 with ECC 3x gold – 2.131 GHz 1x gold prime – 2.419 GHz 4x silver – 1.785 GHz	Octa core Kryo 495 with ECC 4x gold prime – 2.496 GHz 4x silver – 1.7664 GHz
CPU type	Cores and frequency	Cache	Gold – 256 KB L2 per core Silver – 64 KB L2 per core Shared – 1 MB L3	Gold – 256 KB L2 per core Gold prime – 512 KB L2 Silver – 128 KB L2 per core Shared – 2 MB L3	Gold prime – 512 KB L2 per core Silver – 128 KB L2 per core Shared – 4 MB L3
Graphics		Frequency	Qualcomm® Adreno™ 612 845 MHz	Adreno 640 700 MHz	Adreno 680 675 MHz
Memory architecture		Architecture/speed	2 × 16, 1555.2 MHz LPDDR4X	4 × 16, 2092.8 MHz LPDDR4X with ECC	8 × 16, 2092.8 MHz LPDDR4X with ECC
Temperature rating		Junction range	-40°C to 105°C	-40°C to 105°C	-40°C to 105°C
DSP	Audio DSP	Audio processing	Q6 V66K (2 threads/1 cluster,512 KB L2) at 998.4 MHz	Q6 V66J (2 threads/2 clusters, 512 KB L2) at 1.4592 GHz	Q6 V66J (2 threads/2 clusters, 512 KB L2) at 1.4592 GHz
	General purpose DSP	Advanced audio processing		Q6 V66B (2 threads/1 cluster, 1536 KB L2) at 1.4592 GHz	Q6 V66B (2 threads/1 cluster,1536 KB L2) at 1.4592 GHz
	Compute DSP	Compute processing	Q6 V66A (4 threads/2 clusters, 512 KB L2, 2x Qualcomm® Hexagon™ Vector eXtensions(HVX)) at 1.0944 GHz	Q6 V66G (4 threads/2 clusters, 1024 KB L2, 4x HVX) with ECC 1.4592 GHz	Q6 V66G (4 threads/2 clusters, 1024 KB L2, 4x HVX) with ECC 1.4592 GHz
	NPU	Neural processing		NPU130 with ECC 908 MHz	NPU130 with ECC 908 MHz
	Modem DSP	Modem processing	Q6 V66H (4 threads/2 clusters, 1.0 MB L2) at 998.4 MHz	Scalar Q6 V66H (4 threads/2 clusters, 1.5 MB L2) at 1.4592 GHz Vector Q6 V66U (4 threads/ 2 clusters, 512 KB L2) at 1.4592 GHz	Scalar Q6 V66H (4 threads/ 2 clusters, 1.5 MB L2) at 1.4592 GHz Vector Q6 V66U (4 threads/ 2 clusters, 512 KB L2) at 1.4592 GHz
Multimedia	Display	Multiple displays with scalable resolution	2x 1080p + 1x 720p	3x 4K or 4x 2K	3x 5K
	Video	Video decode/encode concurrent	4K60/1080P60 4K30/1080P30	4K120/4K60 4K60/4K30	4K120/4K60 4K60/4K30
	Camera	Multiple concurrent camera input streams	2.5 Gbps/lane up to 30 Gbps total	2.5 Gbps/lane, up to 40 Gbps total	2.5 Gbps/lane, up to 40 Gbps total
Safety			Error-Correction-Coding (ECC)	Safety Element Out of Context (SEooC) targeting assumed system level ASIL-B user cases	Safety Element Out of Context (SEooC) targeting assumed system level ASIL-B user cases

I/O		Description	Snapdragon™ Auto 6155	Snapdragon Auto 8155	Snapdragon Auto 8195
Memory		EBI	LPDDR4X 2x 16 bit 1555 MHz	LPDDR4X 4x 16 bit 2092 MHz	LPDDR4X 8x 16 bit 2092 MHz
		SD/eMMC	SD 3.0 and eMMC 5.1 8-bit SDC1 4-bit SDC2 − −	SD 3.0 − 4-bit SDC2 − 4-bit SDC4	SD 3.0 − 4-bit SDC2 − 4-bit SDC4
		UFS	1 lane UFS 2.1 gear 3	2 lane UFS 2.1 gear 3	2x 2 lane UFS 3.0 gear 4 rate A
		Quad-SPI	1x 4 lane (2x CS)	1x 4 lane (2x CS)	2x 4 lane (2x CS)
Display		DSI	DSI D-PHY v1.2 4-lane DSI0	DSI D-PHY v1.2 4-lane DSI0 4-lane DSI1	DSI D-PHY v1.2 4-lane DSI0 4-lane DSI1
Display		DisplayPort	4-lane DisplayPort v1.4	4-lane DisplayPort v1.4 shared with USB 3.1 Gen 2	3x 4-lane DisplayPort v1.4, 2x shared with USB 3.1 Gen 2 1x 4-lane embedded DisplayPort v1.4b
Camera		CSI	CSI-2 v1.3 4-lane CSI0 4-lane CSI1 4-lane CSI2	CSI-2 v1.3 4-lane CSI0 4-lane CSI1 4-lane CSI2 4-lane CSI3	CSI-2 v1.3 4-lane CSI0 4-lane CSI1 4-lane CSI2 4-lane CSI3
Broadcast		TSIF	Not supported	2x	2x
High-speed interfaces		USB	1x USB 3.1 Gen 1 1x USB 2.0	1x USB 3.1 Gen 2 with DisplayPort 1x USB 3.1 Gen 2	2x USB3.1 Gen 2 with DisplayPort 2x USB3.1 Gen 2
		PCIe	1-lane PCIe 2.0 (RC/EP)	2-lane PCIe 3 (RC/EP) 1-lane PCIe 3 (RC)	1x 1-lane PCIe 3 (RC) 2x 2-lane PCIe 3 (RC) 1x 4-lane PCIe 3 (RC/EP)
		RGMII/RMII	1x with MDIO 1.8 V only	1x with MDIO 1.8 V only	1x with MDIO 1.8 V only
Audio		LS-I2S	4x 2 data lanes 1x 4 data lanes	4x 2 data lanes 1x 4 data lanes	4x 2 data lanes 1x 4 data lanes
		HS-I2S	2x 2 data lanes, receive only	3x 2 data lanes, receive only	3x 2 data lanes, receive only
		TDM/PCM	5x	5x	5x
Miscellaneous		SPI I2C I3C UART	14x QUP SE (GPIO + SSC) SPI – master and slave I 2 C – master UART – host	26x QUP SE (GPIO + SSC) SPI – master and slave I 2 C – master I3C – master UART – host	26x QUP SE (GPIO+SSC) SPI – master and slave I 2 C – master I3C – master UART – host
Miscellaneous		GPIO	155 (GPIO + SSC)	174	190