一、W5500简介
W5500 网络扩展板集成了一个硬件 TCP/IP 协议栈芯片 W5500 以及一个含有网络变压器的 RJ-45（HR911105A）。 其中，W5500 是一款全硬件 TCP/IP 嵌入式以太网控制器，为嵌入式系统提供了更加简易的互联网连接方案， 使用硬件逻辑门电路实现 TCP/IP 协议栈的传输层及网络层（如：TCP, UDP, ICMP, IPv4, ARP, IGMP, PPPoE 等协议）， 并集成了数据链路层，物理层，以及 32K 字节片上 RAM 作为数据收发缓存。使得上位机主控芯片， 只需承担TCP/IP 应用层控制信息的处理任务。从而大大节省了上位机对于数据复制、协议处理和中断处理等方面的工作量，提升了系统利用率及可靠性。
详情：4. w5500模块 — [野火]STM32模块例程介绍 文档 (embedfire.com)
二、厂家Demo演示
二、STM32+W5500+modbus协议编程
下载工程文件并打开
main.c
int main(void)
{
unsigned char i;
/* Initialize STM32F103 */
System_Initialization();//系统配置
SysTick_Init();//启动系统滴答定时器 SysTick
/* Config W5500 */
W5500_Configuration();//W5500配置
Delay_ms(200);//延时等待
/* Modbus-TCP Init */
eMBTCPInit(MB_TCP_PORT_USE_DEFAULT); //端口依赖事件模块初始化
Delay_ms(200); //延时等待
/* Enable Modbus-TCP Stack */
eMBEnable();//激活协议栈
printf("\r\nModbus-TCP Start!\r\n");
printf("IP:192.168.1.128\r\n");
while(1)
{
i=Read_SOCK_1_Byte(0,Sn_SR); //读W5500状态
if(i==0)
{
do
{
Delay_ms(100);//延时等待
}while(Socket_Listen(0)==FALSE);//设置“Socket n”为“TCP服务器模式”
}
else if(i==SOCK_ESTABLISHED) //建立TCP连接
{
eMBPoll();//启动modbus侦听
BSP_LED();//线圈控制LED灯
}
}
}
W5500
/* W5500 configuration */
void W5500_Configuration()
{
unsigned char array[6];
GPIO_SetBits(GPIO_W5500_RST_PORT, GPIO_W5500_RST_Pin);//上拉
Delay_ms(100); /*delay 100ms 使用systick 1ms时基的延时*/
//等待以太网链路
while((Read_1_Byte(PHYCFGR)&LINK)==0); /* Waiting for Ethernet Link */
Write_1_Byte(MR, RST);//写入W5500普通寄存器一个字节
Delay_ms(20); /*delay 20ms */
/* Set Gateway IP as: 192.168.1.1 */
array[0]=192;
array[1]=168;
array[2]=1;
array[3]=1;
Write_Bytes(GAR, array, 4);//设置网关IP
/* Set Subnet Mask as: 255.255.255.0 */
array[0]=255;
array[1]=255;
array[2]=255;
array[3]=0;
Write_Bytes(SUBR, array, 4);//设置子网掩码
/* Set MAC Address as: 0x48,0x53,0x00,0x57,0x55,0x00 */
array[0]=0x48;
array[1]=0x53;
array[2]=0x00;
array[3]=0x57;
array[4]=0x55;
array[5]=0x00;
Write_Bytes(SHAR, array, 6);//设置MAC地址
/* Set W5500 IP as: 192.168.1.128 */
array[0]=192;
array[1]=168;
array[2]=1;
array[3]=128;
Write_Bytes(SIPR, array, 4);//设置W5500的IP地址
}
三、STM32+W5500的web服务
打开工程文件
mian.c
int main(void)
{
Systick_Init(72);//系统时钟初始化
GPIO_Configuration(); //GPIO configuration
USART1_Init(); //串口初始化：115200@8-n-1
printf("W5500 EVB initialization over.\r\n");
Reset_W5500();
WIZ_SPI_Init();//W5500相关引脚配置
printf("W5500 initialized!\r\n");
if(GPIO_ReadInputDataBit(GPIOB,GPIO_Pin_7))
{
DefaultSet();//出厂值
}
else
{
get_config();//read config data from flash
}
printf("Firmware ver%d.%d\r\n",ConfigMsg.sw_ver[0],ConfigMsg.sw_ver[1]);
if(ConfigMsg.debug==0) ConfigMsg.debug=1;
set_network();//配置网络信息
printf("Network is ready.\r\n");
while(1)
{
if(ConfigMsg.JTXD_Control == 0)
do_http();//开启http服务
else
JTXD_do_http();
if(reboot_flag)
NVIC_SystemReset();//发起系统复位请求复位单片机
// reboot();
}
}
W5500
#include <stdio.h>
#include <string.h>
#include "config.h"
#include "SPI2.h"
#include "w5500.h"
#include "socket.h"
#ifdef __DEF_IINCHIP_PPP__
#include "md5.h"
#endif
static uint8 I_STATUS[MAX_SOCK_NUM];
static uint16 SSIZE[MAX_SOCK_NUM]; /**< Max Tx buffer size by each channel */
static uint16 RSIZE[MAX_SOCK_NUM]; /**< Max Rx buffer size by each channel */
uint8 getISR(uint8 s)
{
return I_STATUS[s];
}
void putISR(uint8 s, uint8 val)
{
I_STATUS[s] = val;
}
uint16 getIINCHIP_RxMAX(uint8 s)
{
return RSIZE[s];
}
uint16 getIINCHIP_TxMAX(uint8 s)
{
return SSIZE[s];
}
void IINCHIP_CSoff(void)
{
WIZ_CS(LOW);
}
void IINCHIP_CSon(void)
{
WIZ_CS(HIGH);
}
u8 IINCHIP_SpiSendData(uint8 dat)
{
return(SPI2_SendByte(dat));
}
void IINCHIP_WRITE( uint32 addrbsb, uint8 data)
{
IINCHIP_ISR_DISABLE(); // Interrupt Service Routine Disable
IINCHIP_CSoff(); // CS=0, SPI start
IINCHIP_SpiSendData( (addrbsb & 0x00FF0000)>>16);// Address byte 1
IINCHIP_SpiSendData( (addrbsb & 0x0000FF00)>> 8);// Address byte 2
IINCHIP_SpiSendData( (addrbsb & 0x000000F8) + 4); // Data write command and Write data length 1
IINCHIP_SpiSendData(data); // Data write (write 1byte data)
IINCHIP_CSon(); // CS=1, SPI end
IINCHIP_ISR_ENABLE(); // Interrupt Service Routine Enable
}
uint8 IINCHIP_READ(uint32 addrbsb)
{
uint8 data = 0;
IINCHIP_ISR_DISABLE(); // Interrupt Service Routine Disable
IINCHIP_CSoff(); // CS=0, SPI start
IINCHIP_SpiSendData( (addrbsb & 0x00FF0000)>>16);// Address byte 1
IINCHIP_SpiSendData( (addrbsb & 0x0000FF00)>> 8);// Address byte 2
IINCHIP_SpiSendData( (addrbsb & 0x000000F8)) ;// Data read command and Read data length 1
data = IINCHIP_SpiSendData(0x00); // Data read (read 1byte data)
IINCHIP_CSon(); // CS=1, SPI end
IINCHIP_ISR_ENABLE(); // Interrupt Service Routine Enable
return data;
}
uint16 wiz_write_buf(uint32 addrbsb,uint8* buf,uint16 len)
{
uint16 idx = 0;
if(len == 0) printf("Unexpected2 length 0\r\n");
IINCHIP_ISR_DISABLE();
IINCHIP_CSoff(); // CS=0, SPI start
IINCHIP_SpiSendData( (addrbsb & 0x00FF0000)>>16);// Address byte 1
IINCHIP_SpiSendData( (addrbsb & 0x0000FF00)>> 8);// Address byte 2
IINCHIP_SpiSendData( (addrbsb & 0x000000F8) + 4); // Data write command and Write data length 1
for(idx = 0; idx < len; idx++) // Write data in loop
{
IINCHIP_SpiSendData(buf[idx]);
}
IINCHIP_CSon(); // CS=1, SPI end
IINCHIP_ISR_ENABLE(); // Interrupt Service Routine Enable
return len;
}
uint16 wiz_read_buf(uint32 addrbsb, uint8* buf,uint16 len)
{
uint16 idx = 0;
if(len == 0)
{
printf("Unexpected2 length 0\r\n");
}
IINCHIP_ISR_DISABLE();
//SPI MODE I/F
IINCHIP_CSoff(); // CS=0, SPI start
IINCHIP_SpiSendData( (addrbsb & 0x00FF0000)>>16);// Address byte 1
IINCHIP_SpiSendData( (addrbsb & 0x0000FF00)>> 8);// Address byte 2
IINCHIP_SpiSendData( (addrbsb & 0x000000F8)); // Data write command and Write data length 1
for(idx = 0; idx < len; idx++) // Write data in loop
{
buf[idx] = IINCHIP_SpiSendData(0x00);
}
IINCHIP_CSon(); // CS=1, SPI end
IINCHIP_ISR_ENABLE(); // Interrupt Service Routine Enable
return len;
}
/**
@brief This function is for resetting of the iinchip. Initializes the iinchip to work in whether DIRECT or INDIRECT mode
*/
void iinchip_init(void)
{
setMR( MR_RST );
#ifdef __DEF_IINCHIP_DBG__
printf("MR value is %02x \r\n",IINCHIP_READ_COMMON(MR));
#endif
}
/**
@brief This function set the transmit & receive buffer size as per the channels is used
Note for TMSR and RMSR bits are as follows\n
bit 1-0 : memory size of channel #0 \n
bit 3-2 : memory size of channel #1 \n
bit 5-4 : memory size of channel #2 \n
bit 7-6 : memory size of channel #3 \n
bit 9-8 : memory size of channel #4 \n
bit 11-10 : memory size of channel #5 \n
bit 12-12 : memory size of channel #6 \n
bit 15-14 : memory size of channel #7 \n
Maximum memory size for Tx, Rx in the W5500 is 16K Bytes,\n
In the range of 16KBytes, the memory size could be allocated dynamically by each channel.\n
Be attentive to sum of memory size shouldn't exceed 8Kbytes\n
and to data transmission and receiption from non-allocated channel may cause some problems.\n
If the 16KBytes memory is already assigned to centain channel, \n
other 3 channels couldn't be used, for there's no available memory.\n
If two 4KBytes memory are assigned to two each channels, \n
other 2 channels couldn't be used, for there's no available memory.\n
*/
void sysinit( uint8 * tx_size, uint8 * rx_size )
{
int16 i;
int16 ssum,rsum;
#ifdef __DEF_IINCHIP_DBG__
printf("sysinit()\r\n");
#endif
ssum = 0;
rsum = 0;
for (i = 0 ; i < MAX_SOCK_NUM; i++) // Set the size, masking and base address of Tx & Rx memory by each channel
{
IINCHIP_WRITE( (Sn_TXMEM_SIZE(i)), tx_size[i]);
IINCHIP_WRITE( (Sn_RXMEM_SIZE(i)), rx_size[i]);
#ifdef __DEF_IINCHIP_DBG__
printf("tx_size[%d]: %d, Sn_TXMEM_SIZE = %d\r\n",i, tx_size[i], IINCHIP_READ(Sn_TXMEM_SIZE(i)));
printf("rx_size[%d]: %d, Sn_RXMEM_SIZE = %d\r\n",i, rx_size[i], IINCHIP_READ(Sn_RXMEM_SIZE(i)));
#endif
SSIZE[i] = (int16)(0);
RSIZE[i] = (int16)(0);
if (ssum <= 16384)
{
switch( tx_size[i] )
{
case 1:
SSIZE[i] = (int16)(1024);
break;
case 2:
SSIZE[i] = (int16)(2048);
break;
case 4:
SSIZE[i] = (int16)(4096);
break;
case 8:
SSIZE[i] = (int16)(8192);
break;
case 16:
SSIZE[i] = (int16)(16384);
break;
default :
RSIZE[i] = (int16)(2048);
break;
}
}
if (rsum <= 16384)
{
switch( rx_size[i] )
{
case 1:
RSIZE[i] = (int16)(1024);
break;
case 2:
RSIZE[i] = (int16)(2048);
break;
case 4:
RSIZE[i] = (int16)(4096);
break;
case 8:
RSIZE[i] = (int16)(8192);
break;
case 16:
RSIZE[i] = (int16)(16384);
break;
default :
RSIZE[i] = (int16)(2048);
break;
}
}
ssum += SSIZE[i];
rsum += RSIZE[i];
}
}
// added
/**
@brief This function sets up gateway IP address.
*/
void setGAR(
uint8 * addr /**< a pointer to a 4 -byte array responsible to set the Gateway IP address. */
)
{
wiz_write_buf(GAR0, addr, 4);
}
void getGWIP(uint8 * addr)
{
wiz_read_buf(GAR0, addr, 4);
}
/**
@brief It sets up SubnetMask address
*/
void setSUBR(uint8 * addr)
{
wiz_write_buf(SUBR0, addr, 4);
}
/**
@brief This function sets up MAC address.
*/
void setSHAR(
uint8 * addr /**< a pointer to a 6 -byte array responsible to set the MAC address. */
)
{
wiz_write_buf(SHAR0, addr, 6);
}
/**
@brief This function sets up Source IP address.
*/
void setSIPR(
uint8 * addr /**< a pointer to a 4 -byte array responsible to set the Source IP address. */
)
{
wiz_write_buf(SIPR0, addr, 4);
}
/**
@brief This function sets up Source IP address.
*/
void getGAR(uint8 * addr)
{
wiz_read_buf(GAR0, addr, 4);
}
void getSUBR(uint8 * addr)
{
wiz_read_buf(SUBR0, addr, 4);
}
void getSHAR(uint8 * addr)
{
wiz_read_buf(SHAR0, addr, 6);
}
void getSIPR(uint8 * addr)
{
wiz_read_buf(SIPR0, addr, 4);
}
void setMR(uint8 val)
{
IINCHIP_WRITE(MR,val);
}
/**
@brief This function gets Interrupt register in common register.
*/
uint8 getIR( void )
{
return IINCHIP_READ(IR);
}
/**
@brief This function sets up Retransmission time.
If there is no response from the peer or delay in response then retransmission
will be there as per RTR (Retry Time-value Register)setting
*/
void setRTR(uint16 timeout)
{
IINCHIP_WRITE(RTR0,(uint8)((timeout & 0xff00) >> 8));
IINCHIP_WRITE(RTR1,(uint8)(timeout & 0x00ff));
}
/**
@brief This function set the number of Retransmission.
If there is no response from the peer or delay in response then recorded time
as per RTR & RCR register seeting then time out will occur.
*/
void setRCR(uint8 retry)
{
IINCHIP_WRITE(WIZ_RCR,retry);
}
/**
@brief This function set the interrupt mask Enable/Disable appropriate Interrupt. ('1' : interrupt enable)
If any bit in IMR is set as '0' then there is not interrupt signal though the bit is
set in IR register.
*/
void clearIR(uint8 mask)
{
IINCHIP_WRITE(IR, ~mask | getIR() ); // must be setted 0x10.
}
/**
@brief This sets the maximum segment size of TCP in Active Mode), while in Passive Mode this is set by peer
*/
void setSn_MSS(SOCKET s, uint16 Sn_MSSR)
{
IINCHIP_WRITE( Sn_MSSR0(s), (uint8)((Sn_MSSR & 0xff00) >> 8));
IINCHIP_WRITE( Sn_MSSR1(s), (uint8)(Sn_MSSR & 0x00ff));
}
void setSn_TTL(SOCKET s, uint8 ttl)
{
IINCHIP_WRITE( Sn_TTL(s) , ttl);
}
/**
@brief get socket interrupt status
These below functions are used to read the Interrupt & Soket Status register
*/
uint8 getSn_IR(SOCKET s)
{
return IINCHIP_READ(Sn_IR(s));
}
/**
@brief get socket status
*/
uint8 getSn_SR(SOCKET s)
{
return IINCHIP_READ(Sn_SR(s));
}
/**
@brief get socket TX free buf size
This gives free buffer size of transmit buffer. This is the data size that user can transmit.
User shuold check this value first and control the size of transmitting data
*/
uint16 getSn_TX_FSR(SOCKET s)
{
uint16 val=0,val1=0;
do
{
val1 = IINCHIP_READ(Sn_TX_FSR0(s));
val1 = (val1 << 8) + IINCHIP_READ(Sn_TX_FSR1(s));
if (val1 != 0)
{
val = IINCHIP_READ(Sn_TX_FSR0(s));
val = (val << 8) + IINCHIP_READ(Sn_TX_FSR1(s));
}
} while (val != val1);
return val;
}
/**
@brief get socket RX recv buf size
This gives size of received data in receive buffer.
*/
uint16 getSn_RX_RSR(SOCKET s)
{
uint16 val=0,val1=0;
do
{
val1 = IINCHIP_READ(Sn_RX_RSR0(s));
val1 = (val1 << 8) + IINCHIP_READ(Sn_RX_RSR1(s));
if(val1 != 0)
{
val = IINCHIP_READ(Sn_RX_RSR0(s));
val = (val << 8) + IINCHIP_READ(Sn_RX_RSR1(s));
}
} while (val != val1);
return val;
}
/**
@brief This function is being called by send() and sendto() function also.
This function read the Tx write pointer register and after copy the data in buffer update the Tx write pointer
register. User should read upper byte first and lower byte later to get proper value.
*/
void send_data_processing(SOCKET s, uint8 *data, uint16 len)
{
uint16 ptr =0;
uint32 addrbsb =0;
if(len == 0)
{
printf("CH: %d Unexpected1 length 0\r\n", s);
return;
}
ptr = IINCHIP_READ( Sn_TX_WR0(s) );
ptr = ((ptr & 0x00ff) << 8) + IINCHIP_READ(Sn_TX_WR1(s));
addrbsb = (uint32)(ptr<<8) + (s<<5) + 0x10;
wiz_write_buf(addrbsb, data, len);
ptr += len;
IINCHIP_WRITE( Sn_TX_WR0(s) ,(uint8)((ptr & 0xff00) >> 8));
IINCHIP_WRITE( Sn_TX_WR1(s),(uint8)(ptr & 0x00ff));
}
/**
@brief This function is being called by recv() also.
This function read the Rx read pointer register
and after copy the data from receive buffer update the Rx write pointer register.
User should read upper byte first and lower byte later to get proper value.
*/
void recv_data_processing(SOCKET s, uint8 *data, uint16 len)
{
uint16 ptr = 0;
uint32 addrbsb = 0;
if(len == 0)
{
printf("CH: %d Unexpected2 length 0\r\n", s);
return;
}
ptr = IINCHIP_READ( Sn_RX_RD0(s) );
ptr = ((ptr & 0x00ff) << 8) + IINCHIP_READ( Sn_RX_RD1(s) );
addrbsb = (uint32)(ptr<<8) + (s<<5) + 0x18;
wiz_read_buf(addrbsb, data, len);
ptr += len;
IINCHIP_WRITE( Sn_RX_RD0(s), (uint8)((ptr & 0xff00) >> 8));
IINCHIP_WRITE( Sn_RX_RD1(s), (uint8)(ptr & 0x00ff));
}
void setSn_IR(uint8 s, uint8 val)
{
IINCHIP_WRITE(Sn_IR(s), val);
}
#ifndef _W5500_H_
#define _W5500_H_
#include "Types.h"
/**
@brief Mode Register address
* W5500 SPI Frame consists of 16bits Offset Address in Address Phase,
* 8bits Control Phase and N bytes Data Phase.
* 0 8 16 24 ~
* |----------------|----------------|----------------|----------------------
* | 16bit offset Address | Control Bits | Data Phase
*
* The 8bits Control Phase is reconfigured with Block Select bits (BSB[4:0]),
* Read/Write Access Mode bit (RWB) and SPI Operation Mode (OM[1:0]).
* Block Select bits select a block as like common register, socket register, tx buffer and tx buffer.
* Address value is defined as 16bit offset Address, BSB[4:0] and the three bits of zero-padding.(The RWB and OM [1:0] are '0 'padding)
* Please, refer to W5500 datasheet for more detail about Memory Map.
*
*/
/**
@brief Mode Register address
*/
#define MR (0x000000)
/**
@brief Gateway IP Register address
*/
#define GAR0 (0x000100)
#define GAR1 (0x000200)
#define GAR2 (0x000300)
#define GAR3 (0x000400)
/**
@brief Subnet mask Register address
*/
#define SUBR0 (0x000500)
#define SUBR1 (0x000600)
#define SUBR2 (0x000700)
#define SUBR3 (0x000800)
/**
@brief Source MAC Register address
*/
#define SHAR0 (0x000900)
#define SHAR1 (0x000A00)
#define SHAR2 (0x000B00)
#define SHAR3 (0x000C00)
#define SHAR4 (0x000D00)
#define SHAR5 (0x000E00)
/**
@brief Source IP Register address
*/
#define SIPR0 (0x000F00)
#define SIPR1 (0x001000)
#define SIPR2 (0x001100)
#define SIPR3 (0x001200)
/**
@brief set Interrupt low level timer register address
*/
#define INTLEVEL0 (0x001300)
#define INTLEVEL1 (0x001400)
/**
@brief Interrupt Register
*/
#define IR (0x001500)
/**
@brief Interrupt mask register
*/
#define IMR (0x001600)
/**
@brief Socket Interrupt Register
*/
#define SIR (0x001700)
/**
@brief Socket Interrupt Mask Register
*/
#define SIMR (0x001800)
/**
@brief Timeout register address( 1 is 100us )
*/
#define RTR0 (0x001900)
#define RTR1 (0x001A00)
/**
@brief Retry count reigster
*/
#define WIZ_RCR (0x001B00)
/**
@briefPPP LCP Request Timer register in PPPoE mode
*/
#define PTIMER (0x001C00)
/**
@brief PPP LCP Magic number register in PPPoE mode
*/
#define PMAGIC (0x001D00)
/**
@brief PPP Destination MAC Register address
*/
#define PDHAR0 (0x001E00)
#define PDHAR1 (0x001F00)
#define PDHAR2 (0x002000)
#define PDHAR3 (0x002100)
#define PDHAR4 (0x002200)
#define PDHAR5 (0x002300)
/**
@brief PPP Session Identification Register
*/
#define PSID0 (0x002400)
#define PSID1 (0x002500)
/**
@brief PPP Maximum Segment Size(MSS) register
*/
#define PMR0 (0x002600)
#define PMR1 (0x002700)
/**
@brief Unreachable IP register address in UDP mode
*/
#define UIPR0 (0x002800)
#define UIPR1 (0x002900)
#define UIPR2 (0x002A00)
#define UIPR3 (0x002B00)
/**
@brief Unreachable Port register address in UDP mode
*/
#define UPORT0 (0x002C00)
#define UPORT1 (0x002D00)
/**
@brief PHY Configuration Register
*/
#define PHYCFGR (0x002E00)
/**
@brief chip version register address
*/
#define VERSIONR (0x003900)
/**
@brief socket Mode register
*/
#define Sn_MR(ch) (0x000008 + (ch<<5))
/**
@brief channel Sn_CR register
*/
#define Sn_CR(ch) (0x000108 + (ch<<5))
/**
@brief channel interrupt register
*/
#define Sn_IR(ch) (0x000208 + (ch<<5))
/**
@brief channel status register
*/
#define Sn_SR(ch) (0x000308 + (ch<<5))
/**
@brief source port register
*/
#define Sn_PORT0(ch) (0x000408 + (ch<<5))
#define Sn_PORT1(ch) (0x000508 + (ch<<5))
/**
@brief Peer MAC register address
*/
#define Sn_DHAR0(ch) (0x000608 + (ch<<5))
#define Sn_DHAR1(ch) (0x000708 + (ch<<5))
#define Sn_DHAR2(ch) (0x000808 + (ch<<5))
#define Sn_DHAR3(ch) (0x000908 + (ch<<5))
#define Sn_DHAR4(ch) (0x000A08 + (ch<<5))
#define Sn_DHAR5(ch) (0x000B08 + (ch<<5))
/**
@brief Peer IP register address
*/
#define Sn_DIPR0(ch) (0x000C08 + (ch<<5))
#define Sn_DIPR1(ch) (0x000D08 + (ch<<5))
#define Sn_DIPR2(ch) (0x000E08 + (ch<<5))
#define Sn_DIPR3(ch) (0x000F08 + (ch<<5))
/**
@brief Peer port register address
*/
#define Sn_DPORT0(ch) (0x001008 + (ch<<5))
#define Sn_DPORT1(ch) (0x001108 + (ch<<5))
/**
@brief Maximum Segment Size(Sn_MSSR0) register address
*/
#define Sn_MSSR0(ch) (0x001208 + (ch<<5))
#define Sn_MSSR1(ch) (0x001308 + (ch<<5))
/**
@brief IP Type of Service(TOS) Register
*/
#define Sn_TOS(ch) (0x001508 + (ch<<5))
/**
@brief IP Time to live(TTL) Register
*/
#define Sn_TTL(ch) (0x001608 + (ch<<5))
/**
@brief Receive memory size reigster
*/
#define Sn_RXMEM_SIZE(ch) (0x001E08 + (ch<<5))
/**
@brief Transmit memory size reigster
*/
#define Sn_TXMEM_SIZE(ch) (0x001F08 + (ch<<5))
/**
@brief Transmit free memory size register
*/
#define Sn_TX_FSR0(ch) (0x002008 + (ch<<5))
#define Sn_TX_FSR1(ch) (0x002108 + (ch<<5))
/**
@brief Transmit memory read pointer register address
*/
#define Sn_TX_RD0(ch) (0x002208 + (ch<<5))
#define Sn_TX_RD1(ch) (0x002308 + (ch<<5))
/**
@brief Transmit memory write pointer register address
*/
#define Sn_TX_WR0(ch) (0x002408 + (ch<<5))
#define Sn_TX_WR1(ch) (0x002508 + (ch<<5))
/**
@brief Received data size register
*/
#define Sn_RX_RSR0(ch) (0x002608 + (ch<<5))
#define Sn_RX_RSR1(ch) (0x002708 + (ch<<5))
/**
@brief Read point of Receive memory
*/
#define Sn_RX_RD0(ch) (0x002808 + (ch<<5))
#define Sn_RX_RD1(ch) (0x002908 + (ch<<5))
/**
@brief Write point of Receive memory
*/
#define Sn_RX_WR0(ch) (0x002A08 + (ch<<5))
#define Sn_RX_WR1(ch) (0x002B08 + (ch<<5))
/**
@brief socket interrupt mask register
*/
#define Sn_IMR(ch) (0x002C08 + (ch<<5))
/**
@brief frag field value in IP header register
*/
#define Sn_FRAG(ch) (0x002D08 + (ch<<5))
/**
@brief Keep Timer register
*/
#define Sn_KPALVTR(ch) (0x002F08 + (ch<<5))
/* MODE register values */
#define MR_RST 0x80 /**< reset */
#define MR_WOL 0x20 /**< Wake on Lan */
#define MR_PB 0x10 /**< ping block */
#define MR_PPPOE 0x08 /**< enable pppoe */
#define MR_UDP_FARP 0x02 /**< enbale FORCE ARP */
/* IR register values */
#define IR_CONFLICT 0x80 /**< check ip confict */
#define IR_UNREACH 0x40 /**< get the destination unreachable message in UDP sending */
#define IR_PPPoE 0x20 /**< get the PPPoE close message */
#define IR_MAGIC 0x10 /**< get the magic packet interrupt */
/* Sn_MR values */
#define Sn_MR_CLOSE 0x00 /**< unused socket */
#define Sn_MR_TCP 0x01 /**< TCP */
#define Sn_MR_UDP 0x02 /**< UDP */
#define Sn_MR_IPRAW 0x03 /**< IP LAYER RAW SOCK */
#define Sn_MR_MACRAW 0x04 /**< MAC LAYER RAW SOCK */
#define Sn_MR_PPPOE 0x05 /**< PPPoE */
#define Sn_MR_UCASTB 0x10 /**< Unicast Block in UDP Multicating*/
#define Sn_MR_ND 0x20 /**< No Delayed Ack(TCP) flag */
#define Sn_MR_MC 0x20 /**< Multicast IGMP (UDP) flag */
#define Sn_MR_BCASTB 0x40 /**< Broadcast blcok in UDP Multicating */
#define Sn_MR_MULTI 0x80 /**< support UDP Multicating */
/* Sn_MR values on MACRAW MODE */
#define Sn_MR_MIP6N 0x10 /**< IPv6 packet Block */
#define Sn_MR_MMB 0x20 /**< IPv4 Multicasting Block */
//#define Sn_MR_BCASTB 0x40 /**< Broadcast blcok */
#define Sn_MR_MFEN 0x80 /**< support MAC filter enable */
/* Sn_CR values */
#define Sn_CR_OPEN 0x01 /**< initialize or open socket */
#define Sn_CR_LISTEN 0x02 /**< wait connection request in tcp mode(Server mode) */
#define Sn_CR_CONNECT 0x04 /**< send connection request in tcp mode(Client mode) */
#define Sn_CR_DISCON 0x08 /**< send closing reqeuset in tcp mode */
#define Sn_CR_CLOSE 0x10 /**< close socket */
#define Sn_CR_SEND 0x20 /**< update txbuf pointer, send data */
#define Sn_CR_SEND_MAC 0x21 /**< send data with MAC address, so without ARP process */
#define Sn_CR_SEND_KEEP 0x22 /**< send keep alive message */
#define Sn_CR_RECV 0x40 /**< update rxbuf pointer, recv data */
#ifdef __DEF_IINCHIP_PPP__
#define Sn_CR_PCON 0x23
#define Sn_CR_PDISCON 0x24
#define Sn_CR_PCR 0x25
#define Sn_CR_PCN 0x26
#define Sn_CR_PCJ 0x27
#endif
/* Sn_IR values */
#ifdef __DEF_IINCHIP_PPP__
#define Sn_IR_PRECV 0x80
#define Sn_IR_PFAIL 0x40
#define Sn_IR_PNEXT 0x20
#endif
#define Sn_IR_SEND_OK 0x10 /**< complete sending */
#define Sn_IR_TIMEOUT 0x08 /**< assert timeout */
#define Sn_IR_RECV 0x04 /**< receiving data */
#define Sn_IR_DISCON 0x02 /**< closed socket */
#define Sn_IR_CON 0x01 /**< established connection */
/* Sn_SR values */
#define SOCK_CLOSED 0x00 /**< closed */
#define SOCK_INIT 0x13 /**< init state */
#define SOCK_LISTEN 0x14 /**< listen state */
#define SOCK_SYNSENT 0x15 /**< connection state */
#define SOCK_SYNRECV 0x16 /**< connection state */
#define SOCK_ESTABLISHED 0x17 /**< success to connect */
#define SOCK_FIN_WAIT 0x18 /**< closing state */
#define SOCK_CLOSING 0x1A /**< closing state */
#define SOCK_TIME_WAIT 0x1B /**< closing state */
#define SOCK_CLOSE_WAIT 0x1C /**< closing state */
#define SOCK_LAST_ACK 0x1D /**< closing state */
#define SOCK_UDP 0x22 /**< udp socket */
#define SOCK_IPRAW 0x32 /**< ip raw mode socket */
#define SOCK_MACRAW 0x42 /**< mac raw mode socket */
#define SOCK_PPPOE 0x5F /**< pppoe socket */
/* IP PROTOCOL */
#define IPPROTO_IP 0 /**< Dummy for IP */
#define IPPROTO_ICMP 1 /**< Control message protocol */
#define IPPROTO_IGMP 2 /**< Internet group management protocol */
#define IPPROTO_GGP 3 /**< Gateway^2 (deprecated) */
#define IPPROTO_TCP 6 /**< TCP */
#define IPPROTO_PUP 12 /**< PUP */
#define IPPROTO_UDP 17 /**< UDP */
#define IPPROTO_IDP 22 /**< XNS idp */
#define IPPROTO_ND 77 /**< UNOFFICIAL net disk protocol */
#define IPPROTO_RAW 255 /**< Raw IP packet */
/*********************************************************
* iinchip access function
*********************************************************/
void IINCHIP_WRITE( uint32 addrbsb, uint8 data);
uint8 IINCHIP_READ(uint32 addrbsb);
uint16 wiz_write_buf(uint32 addrbsb,uint8* buf,uint16 len);
uint16 wiz_read_buf(uint32 addrbsb, uint8* buf,uint16 len);
void iinchip_init(void); // reset iinchip
void sysinit(uint8 * tx_size, uint8 * rx_size); // setting tx/rx buf size
uint8 getISR(uint8 s);
void putISR(uint8 s, uint8 val);
uint16 getIINCHIP_RxMAX(uint8 s);
uint16 getIINCHIP_TxMAX(uint8 s);
void setMR(uint8 val);
void setRTR(uint16 timeout); // set retry duration for data transmission, connection, closing ...
void setRCR(uint8 retry); // set retry count (above the value, assert timeout interrupt)
void clearIR(uint8 mask); // clear interrupt
uint8 getIR( void );
void setSn_MSS(SOCKET s, uint16 Sn_MSSR); // set maximum segment size
uint8 getSn_IR(SOCKET s); // get socket interrupt status
uint8 getSn_SR(SOCKET s); // get socket status
uint16 getSn_TX_FSR(SOCKET s); // get socket TX free buf size
uint16 getSn_RX_RSR(SOCKET s); // get socket RX recv buf size
uint8 getSn_SR(SOCKET s);
void setSn_TTL(SOCKET s, uint8 ttl);
void send_data_processing(SOCKET s, uint8 *wizdata, uint16 len);
void recv_data_processing(SOCKET s, uint8 *wizdata, uint16 len);
void setGAR(uint8 * addr); // set gateway address
void setSUBR(uint8 * addr); // set subnet mask address
void setSHAR(uint8 * addr); // set local MAC address
void setSIPR(uint8 * addr); // set local IP address
void getGAR(uint8 * addr);
void getSUBR(uint8 * addr);
void getSHAR(uint8 * addr);
void getSIPR(uint8 * addr);
void setSn_IR(uint8 s, uint8 val);
/**
@brief WIZCHIP_OFFSET_INC on IINCHIP_READ/WRITE
* case1.
* IINCHIP_WRITE(RTR0,val);
* IINCHIP_WRITE(RTR1,val);
* case1.
* IINCHIP_WRITE(RTR0,val);
* IINCHIP_WRITE(WIZCHIP_OFFSET_INC(RTR0,1));
*/
//#define WIZCHIP_OFFSET_INC(ADDR, N) (ADDR + (N<<8)) //< Increase offset address
#endif
参考：(102条消息) STM32+W5500以太网模块_机智的橙子的博客-CSDN博客
版权声明：本文为CSDN博主「dedsec0x」的原创文章，遵循CC 4.0 BY-SA版权协议，转载请附上原文出处链接及本声明。
原文链接：https://blog.csdn.net/dedsec0x/article/details/122147772
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